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? freescale semiconductor, inc., 2009. all rights reserved. freescale semiconductor technical data this document provides an overview of the MPC8377E powerquicc? ii pro processor features, including a block diagram showing the major functional components. the device is a cost-effective, low-power, highly integrated host processor that addresses the requirements of several printing and imaging, consumer, and industrial applications, including main cpus and i/o processors in printing systems, networking switches and line cards, wireless lans (wlans), network access servers (nas), vpn routers, intelligent nic, and industrial controllers. the MPC8377E extends the powerquicc? family, adding higher cpu performance, additional functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size. 1overview the MPC8377E incorporates the e300c4s core, which includes 32 kbytes of l1 instruction and data caches and on-chip memory management units (mmus). the device offers two enhanced three-speed 10, 100, 1000 mbps ethernet interfaces, a ddr1/ddr2 sdram memory controller, a flexible, a 32-bit local bus controller, a 32-bit pci controller, an optional dedi cated security engine, a usb document number: MPC8377Eec rev. 2, 10/2009 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 7 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 4. clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. ddr1 and ddr2 sdram . . . . . . . . . . . . . . . . . . . . 16 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8. ethernet: enhanced three-speed ethernet (etsec) 22 9. usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11. enhanced secure digital host controller (esdhc) . 42 12. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15. pci express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 16. serial ata (sata) . . . . . . . . . . . . . . . . . . . . . . . . . . 67 17. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 18. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 19. ipic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 20. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 21. high-speed serial interfaces (hssi) . . . . . . . . . . . . 76 22. package and pin listings . . . . . . . . . . . . . . . . . . . . . 86 23. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 24. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 25. system design information . . . . . . . . . . . . . . . . . . 117 26. ordering information . . . . . . . . . . . . . . . . . . . . . . . 119 27. document revision history . . . . . . . . . . . . . . . . . . 122 MPC8377E powerquicc ? ii pro processor hardware specifications
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 2 freescale semiconductor overview 2.0 dual-role controller, a progra mmable interrupt controller, dual i 2 c controllers, a 4-channel dma controller, an enhanced secured digital host controlle r, and a general-purpose i/o port. the block diagram of the MPC8377E is shown in figure 1 . figure 1. MPC8377E block diagram and features the following features are supported in the MPC8377E: ? e300c4s core built on power architecture? te chnology with 32-kbyte instruction cache and 32-kbyte data cache, a floating point unit, and two integer units ? ddr1/ddr2 memory controller supporting a 32/64-bit interface ? peripheral interfaces, such as a 32-bit pci interface with up to 66-mhz operation ? 32-bit local bus interface running up to 133-mhz ? usb 2.0 (full/high speed) support ? power management controlle r for low-power consumption ? high degree of software compatibility with previous-generation powerquicc processor-based designs for backward compatibility and easier software migration ? optional security engine provides acceleration for control and data plane security protocols the optional security engine (sec 3.0) is noted with the extension ?e? at the end. it allows cpu-intensive cryptographic operations to be offloaded from the main cpu core. the security-processing accelerator provides hardware acceleration for the des, 3des, aes, sha-1, and md-5 algorithms. MPC8377E security enhanced e300 core 32-kbyte i-cache 32-kbyte d-cache duart dual i 2 c timers gpio spi interrupt controller ddr1/ddr2 sdram controller local bus etsec pci express x1 usb 2.0 hi-speed host device rgmii, rmii, rtbi, mii sata phy phy pci express x1 etsec rgmii, rmii, rtbi, mii dma pci
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 3 overview in addition to the security engine, new high-speed in terfaces such as pci express and sata are included. table 1 compares the differences between mpc837xe derivatives and provides the number of ports available for each interface. 1.1 ddr memory controller the ddr1/ddr2 memory controller includes the following features: ? single 32- or 64-bit interface supporting both ddr1 and ddr2 sdram ? support for up to 400-mhz data rate ? support up to 4 chip selects ? 64-mbit to 2-gbit (for ddr1) and to 4-gbit (for ddr2) devices with 8/ 16/ 32 data ports (no direct 4 support) ? support for up to 32 simultaneous open pages ? supports auto refresh ? on-the-fly power management using cke ? 1.8-/2.5-v sstl2 compatible i/o 1.2 usb dual-role controller the usb controller includes the following features: ? supports usb on-the-go mode, including both device and host functionality, when using an external ulpi (utmi + low-pin interface) phy ? complies with usb specification, rev. 2.0 ? supports operation as a stand-alone usb device ? supports one upstream facing port ? supports three programmable usb endpoints ? supports operation as a stand-alone usb host controller ? supports usb root hub with one downstream-facing port ? enhanced host controller interface (ehci) compatible ? supports high-speed (480 mbps), full-speed (12 mbps), and low-speed (1.5 mbps) operation; low-speed operation is supported only in host mode ? supports utmi + low pin interface (ulpi) table 1. high-speed interfaces on the MPC8377E, mpc8378e, and mpc8379e descriptions MPC8377E mpc8378e mpc8379e sgmii 020 pci express? 2 2 0 sata 204
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 4 freescale semiconductor overview 1.3 dual enhanced three-speed ethernet controllers (etsecs) the etsecs include the following features: ? two enhanced ethernet interfaces can be used for rgmii/mii/rmii/rtbi ? two controllers conform to ieee std 802.3?, ieee 802.3u, ieee 802.3x, ieee 802.3z, ieee 802.3au, ieee 802.3ab, and ieee std 1588? standards ? support for wake-on-magic packet?, a method to bring the device from standby to full operating mode ? mii management interface for external phy control and status 1.4 integrated programmable interrupt controller (ipic) the integrated programmable interrupt controller (ipic) implements the necessary functions to provide a flexible solution for general-purpose interrupt contro l. the ipic programming model is compatible with the mpc8260 interrupt controller, and it supports 8 exte rnal and 34 internal discrete interrupt sources. interrupts can also be redirected to an external interrupt controller. 1.5 power management controller (pmc) the power management controller includes the following features: ? provides power management when the devi ce is used in both host and agent modes ? supports pci power management 1. 2 d0, d1, d2, and d3hot states ? support for pme generation in pci agent mode, pme detection in pci host mode ? supports wake-on-lan (magic packet), usb, gpio, and pci (pme input as host) ? supports mpc8349e backward-compatibility mode 1.6 serial peripheral interface (spi) the serial peripheral interface (spi) allows the device to exchange data between other powerquicc family chips, ethernet phys for configuration, and peripheral devices such as eeproms, real-time clocks, a/d converters, and isdn devices. the spi is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (receive, transmit, clock, and slave select). the spi block consists of transmitter and receiver sections, an independent baud-rate gene rator, and a control unit. 1.7 dma controller, dual i 2 c, duart, enhanced local bus controller (elbc), and timers the device provides an integrated four-channel dma controller with the following features: ? allows chaining (both extended and direct) through local memory-mapped chain descriptors (accessible by local masters) ? supports misaligned transfers
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 5 overview there are two i 2 c controllers. these synchronous, multi-master buses can be connected to additional devices for expansion and system development. the duart supports full-duplex operation and is compatible with the pc16450 and pc16550 programming models. 16-byte fifos are supporte d for both the transmitter and the receiver. the main component of the enhanced local bus contro ller (elbc) is its memory controller, which provides a seamless interface to many types of memory devices and peripherals. the memory controller is responsible for controlling eight memory banks shared by a nand flash control machine (fcm), a general-purpose chip-select machine (gpcm), and up to three user-programmable machines (upms). as such, it supports a minimal glue logic interface to sram, eprom, nor flash eprom, nand flash, eprom, burstable ram, regular dram devices, extended data output dram devices, and other peripherals. the elbc external address latch enable (lale) signal allows multiplexing of addresses with data signals to reduce the device pin count. the enhanced local bus controller also includes a num ber of data checking and protection features, such as data parity generation and checki ng, write protection, and a bus monitor to ensure that each bus cycle is terminated within a user-specified period. the local bus can operate at up to 133 mhz. the system timers include the following features: periodic interrupt timer, real time clock, software watchdog timer, and two gene ral-purpose timer blocks. 1.8 security engine the optional security engine is optimized to handle all the algorithms associated with ipsec, ieee 802.11i, and iscsi. the security engine contains one crypto-channel, a controller, and a set of crypto execution units (eus). the execution units are: ? data encryption standard execution unit (deu), supporting des and 3des ? advanced encryption standard unit (aesu), supporting aes ? message digest execution unit (mdeu), supporting md5, sha1, sha-256, and hmac with any algorithm ? one crypto-channel supporting multi-command descriptor chains 1.9 pci controller the pci controller includes the following features: ? pci specification revision 2.3 compatible ? single 32-bit data pci interface operates at up to 66 mhz ? pci 3.3-v compatible (not 5-v compatible) ? support for host and agent modes ? on-chip arbitration, supporting 5 external masters on pci ? selectable hardware-enforced coherency
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 6 freescale semiconductor overview 1.10 pci express? controller the pci express? controller includes the following features: ? pci express 1.0a compatible ?two 1 links or one 2 link width ? auto-detection of number of connected lanes ? selectable operation as root complex or endpoint ? both 32- and 64-bit addressing ? 128-byte maximum payload size ? support for msi and intx interrupt messages ? virtual channel 0 only ? selectable traffic class ? full 64-bit decode with 32-bit wide windows ? dedicated four channel descriptor-based dma engine per interface 1.11 serial ata (sata) controllers the serial ata (sata) controllers have the following features: ? supports serial ata rev 2.5 specification ? spread spectrum clocking on receive ? asynchronous notification ? hot plug including asynchronous signal recovery ? link power management ? native command queuing ? staggered spin-up and port multiplier support ? port multiplier support ? sata 1.5 and 3.0 gb/s operation ? interrupt driven ? power management support ? error handling and diagnostic features ? far end/near end loopback ? failed crc error reporting ? increased align insertion rates ? scrambling and cont override 1.12 enhanced secured digital host controller (esdhc) the enhanced sd host controller (esdhc) has the following features: ? conforms to sd host controller standard specification, rev 2. 0 with test event register support. ? compatible with the mmc system specification, rev 4.0
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 7 electrical characteristics ? compatible with the sd memory card specification, rev 2.0 , and supports high capacity sd memory cards ? compatible with the sdio card specification rev, 1.2 ? designed to work with sd memory, minisd memory, sdio, minisdio, sd combo, mmc, mmc plus , mmc 4x, and rs-mmc cards ? sd bus clock frequency up to 50 mhz ? supports 1-/4-bit sd and sdio modes, 1-/4-bit mmc modes ? supports internal dma capabilities 2 electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the MPC8377E. the device is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications. 2.1 overall dc electrical characteristics this section covers the ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings table 2 provides the absolute maximum ratings. table 2. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage v dd ?0.3 to 1.1 v ? pll supply voltage (e300 core, system and elbc) av dd ?0.3 to 1.1 v ? ddr1 and ddr2 dram i/o voltage gv dd ?0.3 to 2.75 ?0.3 to 1.98 v? three-speed ethernet i/o, mii management voltage lv dd [1,2] ?0.3 to 3.63 v ? pci, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd ?0.3 to 3.63 v ? local bus lbv dd ?0.3 to 3.63 v ? serdes l[1,2]_ n v dd ?0.3 to 1.1 v 6 input voltage ddr dram signals mv in ?0.3 to (gv dd + 0.3) v 2, 4 ddr dram reference mv ref ?0.3 to (gv dd + 0.3) v 2, 4 three-speed ethernet signals lv in ?0.3 to (lv dd + 0.3) v ? pci, duart, clkin, system control and power management, i 2 c, and jtag signals ov in ?0.3 to (ov dd + 0.3) v 3, 4 local bus lb in ?0.3 to (lbv dd + 0.3) v 5
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 8 freescale semiconductor electrical characteristics 2.1.2 power supply voltage specification table 3 provides the recommended operating conditions fo r the device. note that the values in table 3 are the recommended and tested operating conditions. prope r device operation outside of these conditions is not guaranteed. storage temperature range t stg ?55 to 150 c? notes: 1 functional and tested operating conditions are given in ta b l e 3 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2 caution: mv in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3 caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4 (m,o)v in and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 . 5 ov in on the pci interface may overshoot/undershoot according to the pci electrical specification for 3.3-v operation, as shown in figure 2 . 6 l[1,2]_ n v dd includes sdav dd _0, xcorev dd , and xpadv dd power inputs. table 3. recommended operating conditions characteristic symbol recommended value unit notes core supply voltage up to 667 mhz v dd 1.0 50 mv v 1 800 mhz 1.05 50 mv v 1 pll supply voltage (e300 core, system, and elbc) up to 667 mhz av dd 1.0 50 mv v 1 800 mhz 1.05 50 mv v 1 ddr1 and ddr2 dram i/o voltage gv dd 2.5 v 125 mv 1.8 v 90 mv v1 three-speed ethernet i/o, mii management voltage lv dd [1,2] 3.3 v 165 mv 2.5 v 125 mv v? pci, local bus, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd 3.3 v 165 mv v 1 local bus lbv dd 1.8 v 90 mv 2.5 v 125 mv 3.3 v 165 mv v? serdes up to 667 mhz l[1,2]_ n v dd 1.0 50 mv v 1, 2 800 mhz 1.05 v 50 mv v 1, 2 table 2. absolute maximum ratings 1 (continued) characteristic symbol max value unit notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 9 electrical characteristics figure 2 shows the undershoot and overshoot voltages at the interfaces of the device. figure 2. overshoot/undershoot voltage for gv dd /ov dd /lv dd operating temperature range commerical t a t j t a =0 (min)? t j =125 (max) c? extended temperature t a t j t a =?40 (min)? t j =125 (max) c? notes: 1 gv dd , ov dd , av dd , and v dd must track each other and must vary in the same direction?either in the positive or negative direction. 2 l[1,2]_ n v dd , sdav dd _0, xcorev dd , and xpadv dd power inputs. table 3. recommended operating conditions (continued) characteristic symbol recommended value unit notes gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/l/o vdd + 20% g/l/o vdd g/l/o vdd + 5% of tinterface1 1. note that t interface refers to the clock period associated with the bus clock interface. v ih v il note: 2. please note that with the pci overshoot allowed (as specified above), the device does not fully comply with the maximum ac ratings and device protection guideline outlined in the pci rev. 2.3 specification (section 4.2.2.3).
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 10 freescale semiconductor electrical characteristics 2.1.3 output driver characteristics table 4 provides information on the characteristics of the output driver strengths. the values are preliminary estimates. 2.2 power sequencing the device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. during the power ramp up, before the power supplies are stable and if the i/o voltages are supplied before the core voltage, th ere may be a period of time that al l input and output pins will actively be driven and cause contention and excessive curren t. to avoid actively driving the i/o pins and to eliminate excessive current draw, apply the core voltages (v dd and av dd ) before the i/o voltages and assert poreset before the power supplies fully ramp up. v dd and av dd must reach 90% of their nominal value before gv dd , lv dd , and ov dd reach 10% of their value, see figure 3 . i/o voltage supplies, gv dd , lv dd , and ov dd do not have any ordering requirement s with respect to one another. figure 3. power-up sequencing example table 4. output drive capability driver type 1 1 specialized serdes output capabilities are described in the relevant sections of these specifications (such as pci express and sata) output impedance ( ) supply voltage local bus interface utilities signals 45 lbv dd = 2.5 v, 3.3 v 40 lbv dd = 1.8 v pci signals 25 ov dd = 3.3 v ddr1 signal 18 gv dd = 2.5 v ddr2 signal 18 gv dd = 1.8 v etsec 10/100/1000 signals 45 lv dd = 2.5 v, 3.3 v duart, system control, i 2 c, jtag, spi, and usb 45 ov dd = 3.3 v gpio signals 45 ov dd = 3.3 v t 90% v core voltage (vdd , avdd) i/o voltage (gvdd, lvdd, and ovdd) 0 0.7 v
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 11 power characteristics please note that the serdes power supply (l[1,2]_ n v dd ) should follow the same timing as the core supply (v dd ). the opposite sequence applies to the power down requi rements. the i/o supplies must go down first and immediately followed by the core and pll supplies. 3 power characteristics the estimated typical power dissipation for the MPC8377E device is shown in table 5 . table 5. MPC8377E power dissipation 1 core frequency (mhz) csb/ddr frequency (mhz) sleep power at t j =65 c (w) 2 typical application at t j =65 c (w) 2 typical application at t j =125 c (w) 3 max application at t j =125 c (w) 4 333 333 1.45 1.9 3.2 3.8 167 1.45 1.8 3.0 3.6 400 400 1.45 2.0 3.3 4.0 266 1.45 1.9 3.1 3.8 450 300 1.45 2.0 3.2 3.8 225 1.45 1.9 3.1 3.7 500 333 1.45 2.0 3.3 3.9 250 1.45 1.9 3.2 3.8 533 355 1.45 2.0 3.3 4.0 266 1.45 2.0 3.2 3.9 600 400 1.45 2.1 3.4 4.1 300 1.45 2.0 3.3 4.0 667 333 1.45 2.1 3.3 4.1 266 1.45 2.0 3.3 3.9 800 400 1.45 2.5 3.8 4.3 note: 1 the values do not include i/o supply power (ov dd , lv dd , gv dd ) or av dd . for i/o power values, see tab le 6 . 2 typical power is based on a voltage of v dd = 1.0 v for core frequences 667 mhz or v dd = 1.05 v for core frequences of 800 mhz, and running a dhrystone benchmark application. 3 typical power is based on a voltage of v dd = 1.0 v for core frequences 667 mhz or v dd = 1.05 v for core frequences of 800 mhz, and running a dhrystone benchmark application. 4 maximum power is based on a voltage of v dd = 1.0 v for core frequences 667 mhz or v dd = 1.05 v for core frequences of 800 mhz, worst case process, and running an artificial smoke test.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 12 freescale semiconductor power characteristics table 6 shows the estimated typical i/o power dissipation for the device. table 6. MPC8377E typical i/o power dissipation interface parameter gv dd (1.8 v) gv dd /lbv dd (2.5 v) ov dd (3.3 v) lv dd (3.3 v) lv dd (2.5 v) l[1,2]_ n v dd (1.0 v) unit comments ddr i/o 65% utilization 2 pair of clocks 200 mhz data rate, 32-bit 0.28 0.35 ? ? ? ? w ? 200 mhz data rate, 64-bit 0.41 0.49 ? ? ? ? w 266 mhz data rate, 32-bit 0.31 0.4 ? ? ? ? w 266 mhz data rate, 64-bit 0.46 0.56 ? ? ? ? w 300 mhz data rate, 32-bit 0.33 0.43 ? ? ? ? w 300 mhz data rate, 64-bit 0.48 0.6 ? ? ? ? w 333 mhz data rate, 32-bit 0.35 0.45 ? ? ? ? w 333 mhz data rate, 64-bit 0.51 0.64 ? ? ? ? w 400 mhz data rate, 32-bit 0.38 ? ? ? ? ? w 400 mhz data rate, 64-bit 0.56 ? ? ? ? ? w pci i/o load = 30 pf 33 mhz, 32-bit ? ? 0.04 ? ? ? w ? 66 mhz, 32-bit ? ? 0.07 ? ? ? w local bus i/o load = 25 pf 167 mhz, 32-bit 0.09 0.17 0.29 ? ? ? w ? 133 mhz, 32-bit 0.07 0.14 0.24 ? ? ? w 83 mhz, 32-bit 0.05 0.09 0.15 ? ? ? w 66 mhz, 32-bit 0.04 0.07 0.13 ? ? ? w 50 mhz, 32-bit 0.03 0.06 0.1 ? ? ? w
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 13 clock input timing 4 clock input timing this section provides the clock input dc and ac el ectrical characteristics for the MPC8377E. note that the pci_clk/pci_sync_in signal or clkin signal is used as the pci input clock depending on whether the device is configured as a host or agent de vice. clkin is used when the device is in host mode. 4.1 dc electrical characteristics table 7 provides the clock input (clkin/pci_clk ) dc timing specifications for the device. etsec i/o load = 25 pf mii or rmii ? ? ? 0.02 ? ? w multiply by number of interfaces used. rgmii or rtbi ? ? ? ? 0.05 ? w ? usb (60mhz clock) 12 mbps ? ? 0.01 ? ? ? w ? 480 mbps ? ? 0.2 ? ? ? w serdes per lane ? ? ? ? 0.029 w ? other i/o ? ? ? 0.01 ? ? ? w ? note: the values given are for typical, and not worst case, switching. table 7. clkin dc electrical characteristics parameter condition symbol min max unit notes input high voltage ? v ih 2.7 ov dd + 0.3 v 1 input low voltage ? v il ?0.3 0.4 v 1 clkin input current 0 v v in ov dd i in ? 10 a? pci_clk input current 0 v v in 0.5 v or ov dd ? 0.5 v v in ov dd i in ? 30 a? note: 1 in pci agent mode, this specification does not comply with pci 2.3 specification . table 6. MPC8377E typical i/o power dissipation (continued) interface parameter gv dd (1.8 v) gv dd /lbv dd (2.5 v) ov dd (3.3 v) lv dd (3.3 v) lv dd (2.5 v) l[1,2]_ n v dd (1.0 v) unit comments
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 14 freescale semiconductor reset initialization 4.2 ac electrical characteristics the primary clock source for the device can be one of two inputs, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. table 8 provides the clock input (clkin/pci_clk) ac timing specifications for the device. 5 reset initialization this section describes the dc and ac electrical specifications for the reset initialization timing and electrical requirements of the MPC8377E. 5.1 reset dc electrical characteristics table 9 provides the dc electrical characteristics for the reset pins of the device. table 8. clkin ac timing specifications parameter symbol min typical max unit notes clkin/pci_clk frequency f clkin 25 ? 66.666 mhz 1, 6 clkin/pci_clk cycle time t clkin 15 ? 40 ns ? clkin/pci_clk rise and fall time t kh , t kl 0.6 1.0 2.3 ns 2 clkin/pci_clk duty cycle t khk /t clkin 40 ? 60 % 3 clkin/pci_clk jitter ? ? ? 150 ps 4, 5 notes: 1 caution: the system, core and security block must not exceed their respective maximum or minimum operating frequencies. 2 rise and fall times for clkin/pci_clk are measured at 0.4 v and 2.7 v. 3 timing is guaranteed by design and characterization. 4 this represents the total input jitter-short term and long term-and is guaranteed by design. 5 the clkin/pci_clk driver?s closed loop jitter bandwidth should be <500 khz at -20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track clkin drivers with the specified jitter. 6 spread spectrum is allowed up to 1% down-spread on clkin/pci_clk up to 60 khz. table 9. reset pins dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih ?2.0ov dd + 0.3 v input low voltage v il ? ?0.3 0.8 v input current i in ?? 30 a output high voltage v oh i oh = ? 8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v note: ? this table applies for pins poreset and hreset . the poreset is input pin, thus stated output voltages are not relevant. ? hreset and sreset are open drain pin, thus v oh is not relevant for these pins.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 15 reset initialization 5.2 reset ac electrical characteristics table 10 provides the reset initialization ac timing specifications of the device. table 11 provides the pll lock times. table 10. reset initialization timing specifications parameter/condition min max unit notes required assertion time of hreset to activate reset flow 32 ? t pci_sync_in 1 required assertion time of poreset with stable clock applied to clkin when the device is in pci host mode 32 ? t clkin 2 required assertion time of poreset with stable clock applied to pci_clk when the device is in pci agent mode 32 ? t pci_sync_in 1 hreset assertion (output) 512 ? t pci_sync_in 1 hreset negation to negation (output) 16 ? t pci_sync_in 1 input setup time for por config signals (cfg_reset_source[0:3], cfg_clkin_div, and cfg_lbmux) with respect to negation of poreset when the device is in pci host mode 4? t clkin 2 input setup time for por config signals (cfg_reset_source[0:3], cfg_clkin_div, and cfg_lbmux) with respect to negation of poreset when the device is in pci agent mode 4?t pci_sync_in 1 input hold time for por config signals with respect to negation of hreset 0? ns ? time for the device to turn off por config signals with respect to the assertion of hreset ?4 ns 3 time for the device to start driving functional output signals multiplexed with the por configuration signals with respect to the negation of hreset 1?t pci_sync_in 1, 3 note: 1 t pci_sync_in is the clock period of the input clock applied to pci_sync_in. when the device is in pci host mode the primary clock is applied to the clkin input, and pci_sync_in period depends on the value of cfg_clkin_div. see the mpc8379e integrated host processor reference manual for more details. 2 t clkin is the clock period of the input clock applied to clkin. it is only valid when the device is in pci host mode. see the mpc8379e integrated host processor reference manual for more details. 3 por config signals consists of cfg_reset_source[0:3], cfg_lbmux, and cfg_clkin_div. table 11. pll lock times parameter min max unit notes pll lock times ? 100 s? note: ? the device guarantees the pll lock if the clock settings are within spec range. the core clock also depends on the core pll ratio. see section 23, ?clocking,? for more information.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 16 freescale semiconductor ddr1 and ddr2 sdram 6 ddr1 and ddr2 sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the MPC8377E. note that ddr1 sdram is gv dd (typ) = 2.5 v and ddr2 sdram is gv dd (typ) = 1.8 v. 6.1 ddr1 and ddr2 sdram dc electrical characteristics table 12 provides the recommended operating conditions for the ddr2 sdram component(s) of the device when gv dd (typ) = 1.8 v . table 13 provides the ddr2 capacitance when gv dd (typ) = 1.8 v. table 12. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8 v parameter symbol min max unit notes i/o supply voltage gv dd 1.71 1.89 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2, 5 i/o termination voltage v tt mv ref ?0.04 mv ref +0.04 v 3 input high voltage v ih mv ref + 0.140 gv dd +0.3 v ? input low voltage v il ?0.3 mv ref ? 0.140 v ? output leakage current i oz ?40 40 a4 output high current (v out =1.40v) i oh ?13.4 ? ma ? output low current (v out =0.3v) i ol 13.4 ? ma ? note: 1 gv dd is expected to be within 50 mv of the dram gv dd at all times. 2 mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3 v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4 output leakage is measured with all outputs disabled, 0 v v out gv dd . 5 see an3665, mpc837xe design checklist , for proper ddr termination. table 13. ddr2 sdram capacitance for gv dd (typ) = 1.8 v parameter symbol min max unit notes input/output capacitance: dq, dqs, dqs c io 68pf1 delta input/output capacitance: dq, dqs, dqs c dio ?0.5pf1 note: 1 this parameter is sampled. gv dd = 1.8 v 0.090 v, f = 1 mhz, t a =25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 17 ddr1 and ddr2 sdram table 14 provides the recommended operating conditions for the ddr sdram component(s) when gv dd (typ) = 2.5 v . table 15 provides the ddr capacitance when gv dd (typ) = 2.5 v. table 16 provides the current draw characteristics for mv ref . table 14. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5 v parameter symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2, 5 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.18 gv dd + 0.3 v ? input low voltage v il ?0.3 mv ref ? 0.18 v ? output leakage current i oz ?40 40 a4 output high current (v out = 1.9 v) i oh ?15.2 ? ma ? output low current (v out = 0.38 v) i ol 15.2 ? ma ? note: 1 gv dd is expected to be within 50 mv of the dram gv dd at all times. 2 mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3 v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4 output leakage is measured with all outputs disabled, 0 v v out gv dd . 5 see an3665, mpc837xe design checklist , for proper ddr termination. table 15. ddr sdram capacitance for gv dd (typ) = 2.5 v parameter symbol min max unit notes input/output capacitance: dq, dqs c io 68pf1 delta input/output capacitance: dq, dqs c dio ?0.5pf1 note: 1 this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a = 25c, v out =gv dd /2, v out (peak-to-peak) = 0.2 v. table 16. current draw characteristics for mv ref parameter symbol min typ max unit note current draw for mv ref ddr1 ddr2 i mvref ? ? 250 150 600 400 a1, 2 note: 1 the voltage regulator for mv ref must be able to supply up to the stated maximum current. 2 this current is divided equally between mvref1 and mvref2, where half the current flows through each pin.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 18 freescale semiconductor ddr1 and ddr2 sdram 6.2 ddr1 and ddr2 sdram ac electrical characteristics this section provides the ac electrical characteristics for the ddr sdram interface. 6.2.1 ddr1 and ddr2 sdram input ac timing specifications table 17 provides the input ac timing specifications for the ddr2 sdram when g vdd(typ) = 1.8 v. table 18 provides the input ac timing specifications for the ddr1 sdram when gv dd (typ) = 2.5 v. table 19 provides the input ac timing specifications for the ddr1 and ddr2 sdram interface. table 17. ddr2 sdram input ac timing specifications for 1.8-v interface parameter symbol min max unit ac input low voltage v il ?mv ref ? 0.25 v ac input high voltage v ih mv ref + 0.25 ? v table 18. ddr1 sdram input ac timing specifications for 2.5-v interface parameter symbol min max unit ac input low voltage v il ?mv ref ? 0.31 v ac input high voltage v ih mv ref + 0.31 ? v table 19. ddr1 and ddr2 sdram input ac timing specifications parameter symbol min max unit notes controller skew for mdqs-mdq/mecc/mdm 400 mhz data rate 333 mhz data rate 266 mhz data rate t ciskew ?500 ?750 ?750 500 750 750 ps 1, 2 3 ? ? note: 1 t ciskew represents the total amount of skew consumed by the controller between mdqs n and any corresponding bit that will be captured with mdqs n . this should be subtracted from the total timing budget. 2 the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew . this can be determined by the following equation: t diskew = [t/4 ? |t ciskew |] where t is the mck clock period and |t ciskew | is the absolute value of t ciskew . 3 this specification applies only to ddr2 interface.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 19 ddr1 and ddr2 sdram 6.2.2 ddr1 and ddr2 sdram output ac timing specifications table 20 shows the ddr1 and ddr2 sdram output ac timing specifications. table 20. ddr1 and ddr2 sdram output ac timing specifications parameter symbol 1 min max unit notes mck n cycle time, mck n /mck n crossing t mck 510ns2 addr/cmd output setup with respect to mck 400 mhz data rate 333 mhz data rate 266 mhz data rate 200 mhz data rate t ddkhas 1.95 2.40 3.15 4.20 ? ? ? ? ns 3, 7 addr/cmd output hold with respect to mck 400 mhz data rate 333 mhz data rate 266 mhz data rate 200 mhz data rate t ddkhax 1.95 2.40 3.15 4.20 ? ? ? ? ns 3, 7 mcs n output setup with respect to mck 400 mhz data rate 333 mhz data rate 266 mhz data rate 200 mhz data rate t ddkhcs 1.95 2.40 3.15 4.20 ? ? ? ? ns 3 mcs n output hold with respect to mck 400 mhz data rate 333 mhz data rate 266 mhz data rate 200 mhz data rate t ddkhcx 1.95 2.40 3.15 4.20 ? ? ? ? ns 3 mck to mdqs skew t ddkhmh ? 0.6 0.6 ns 4, 8 mdq//mdm output setup with respect to mdqs 400 mhz data rate 333 mhz data rate 266 mhz data rate 200 mhz data rate t ddkhds, t ddklds 550 800 1100 1200 ? ? ? ? ps 5, 8 mdq//mdm output hold with respect to mdqs 400 mhz data rate 333 mhz data rate 266 mhz data rate 200 mhz data rate t ddkhdx, t ddkldx 700 800 1100 1200 ? ? ? ? ps 5, 8 mdqs preamble start t ddkhmp ? 0.5 t mck ?0.6 ? 0.5 t mck + 0.6 ns 6, 8
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 20 freescale semiconductor ddr1 and ddr2 sdram the minimum frequency for ddr2 is 250 mhz data ra te (125 mhz clock), 167 mhz data rate (83 mhz clock) for ddr1. figure 4 shows the ddr1 and ddr2 sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 4. ddr timing diagram for t ddkhmh mdqs epilogue end t ddkhme ? 0.6 0.6 ns 6, 8 note: 1 the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2 all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3 addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq//mdm/mdqs. 4 note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck[n] clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 register. this will typically be set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. see the mpc8379e powerquicc ii pro host processor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5 determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data mdq, ecc, or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6 all outputs are referenced to the rising edge of mck n at the pins of the microprocessor. note that t ddkhmp follows the symbol conventions described in note 1. 7 clock control register is set to adjust the memory clocks by 1/2 the applied cycle. 8 see an3665, ?mpc837xe design checklist,? for proper ddr termination. table 20. ddr1 and ddr2 sdram output ac timing specifications (continued) parameter symbol 1 min max unit notes mdqs mck [n] mck[n] t mck t ddkhmhmax) = 0.6 ns t ddkhmh(min) = ?0.6 ns mdqs
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 21 duart figure 5 shows the ddr1 and ddr2 sdram output timing diagram. figure 5. ddr1 and ddr2 sdram output timing diagram figure 6 provides the ac test load for the ddr bus. figure 6. ddr ac test load 7duart this section describes the dc and ac electri cal specifications for the duart interface of the MPC8377E. 7.1 duart dc electrical characteristics table 21 provides the dc electrical characteristics for the duart interface of the device. table 21. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage ov dd v il ?0.3 0.8 v addr/cmd t ddkhas ,t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax ,t ddkhcx write a0 noop t ddkhme t ddkhmp output z 0 = 50 r l = 50 gvdd/2
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 22 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec) 7.2 duart ac electrical specifications table 22 provides the ac timing parameters for the duart interface of the device. 8 ethernet: enhanced three-speed ethernet (etsec) this section provides the ac and dc electrical char acteristics for the enhanced three-speed ethernet controller. 8.1 enhanced three-speed ethernet controller (etsec) (10/100/1000 mbps)?mii/rgmii/rtbi/rmii dc electrical characteristics the electrical characteristics specified here apply to media independent interface (mii), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), reduced media independent interface (rmii) signals, management data input/ output (mdio) and manage ment data clock (mdc). the mii and rmii interfaces are defined for 3.3 v, while the rgmii and rtbi interfaces can be operated at 2.5 v. the rgmii and rtbi interfaces follow the reduced gigabit media-independent interface (rgmii) specification version 1.3 . the rmii interface follows the rmii consortium rmii specification version 1.2 . high-level output voltage, i oh = ?100 a v oh ov dd ? 0.2 ? v low-level output voltage, i ol = 100 a v ol ?0.2 v input current, (0 v v in ov dd ) i in ?30 a note: ? the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 2 . table 22. duart ac timing specifications parameter value unit notes minimum baud rate 256 baud ? maximum baud rate > 1,000,000 baud 1 oversample rate 16 ? 2 notes: 1 actual attainable baud rate will be limited by the latency of interrupt processing. 2 the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample. table 21. duart dc electrical characteristics (continued)
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 23 ethernet: enhanced three-speed ethernet (etsec) 8.1.1 mii, rmii, rgmii, and rtbi dc electrical characteristics mii and rmii drivers and receivers comply with the dc parametric attributes specified in table 23 and table 24 . the rgmii and rtbi signals in table 24 are based on a 2.5 v cmos interface voltage as defined by jedec eia/jesd8-5. table 23. mii and rmii dc electrical characteristics parameter symbol min max unit notes supply voltage 3.3 v lv dd1 lv dd2 3.13 3.47 v output high voltage (lv dd1 /lv dd2 = min, i oh = ?4.0 ma) v oh 2.40 lv dd1 /lv dd2 + 0.3 v ? output low voltage (lv dd1 /lv dd2 = min, i ol = 4.0 ma) v ol gnd 0.50 v ? input high voltage v ih 2.0 lv dd1 /lv dd2 + 0.3 v ? input low voltage v il ?0.3 0.90 v ? input high current (v in = lv dd1 , v in = lv dd2 ) i ih ?30 a input low current (v in = gnd) i il ?600 ? a? note: 1. lv dd1 supports etsec 1. lv dd2 supports etsec 2. table 24. rgmii and rtbi dc electrical characteristics parameter symbol min max unit notes supply voltage 2.5 v lv dd1 lv dd2 2.37 2.63 v 1, 2 output high voltage (lv dd1 /lv dd2 = min, ioh = ?1.0 ma) v oh 2.00 lv dd1 /lv dd2 + 0.3 v ? output low voltage (lv dd1 /lv dd2 = min, i ol = 1.0 ma) v ol gnd ? 0.3 0.40 v ? input high voltage v ih 2.0 lv dd1 /lv dd2 + 0.3 v ? input low voltage v il ?0.3 0.70 v ? input high current (v in = lv dd1 , v in = lv dd2 ) i ih ??20 a1, 2 input low current (v in = gnd) i il ?20 ? a? note: 1 lv dd1 supports etsec 1. 2 lv dd2 supports etsec 2.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 24 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec) 8.2 mii, rgmii, rmii, and rtbi ac timing specifications the ac timing specifications for mii, rgmii, rmii and rtbi are presented in this section. 8.2.1 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 8.2.1.1 mii transmit ac timing specifications table 25 provides the mii transmit ac timing specifications. figure 7 shows the mii transmit ac timing diagram. figure 7. mii transmit ac timing diagram table 25. mii transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter symbol 1 1 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). min typical max unit tx_clk clock period 10 mbps t mtx ? 400 ? ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise (20%-80%) t mtxr 1.0 ? 4.0 ns tx_clk data clock fall (80%-20%) t mtxf 1.0 ? 4.0 ns note: tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 25 ethernet: enhanced three-speed ethernet (etsec) 8.2.1.2 mii receive ac timing specifications table 26 provides the mii receive ac timing specifications. figure 8 provides the ac test load for etsec. figure 8. etsec ac test load table 26. mii receive ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter symbol 1 1 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). min typical max unit input low voltage v il ??0.7v input high voltage v ih 1.9 ? ? v rx_clk clock period 10 mbps t mrx ? 400 ? ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise (20%-80%) t mrxr 1.0 ? 4.0 ns rx_clk clock fall time (80%-20%) t mrxf 1.0 ? 4.0 ns note: output z 0 = 50 lvdd/2 r l = 50
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 26 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec) figure 9 shows the mii receive ac timing diagram. figure 9. mii receive ac timing diagram 8.2.2 rgmii and rtbi ac timing specifications table 27 presents the rgmii and rtbi ac timing specifications. table 27. rgmii and rtbi ac timing specifications at recommended operating conditions with lv dd of 2.5 v 5%. parameter/condition symbol 1 min typical max unit notes data to clock output skew (at transmitter) t skrgt ?600 0 600 ps ? data to clock input skew (at receiver) t skrgt 1.0 ? 2.8 ns 2 clock period t rgt 7.2 8.0 8.8 ns 3 duty cycle for 1000base-t t rgth /t rgt 45 50 55 % 4 duty cycle for 10base-t and 100base-tx t rgth /t rgt 40 50 60 % 3, 4 rise time (20%?80%) t rgtr ? ? 0.75 ns ? fall time (20%?80%) t rgtf ? ? 0.75 ns ? ec_gtx_clk125 reference clock period t g12 ?8.0?ns5 ec_gtx_clk125 reference clock duty cycle measured at 0.5 lv dd1 t g125h /t g125 47 ? 53 % ? note: 1 note that, in general, the clock reference symbol representation for this section is based on the symbols rgt to represent rgmii and rtbi timing. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2 this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3 for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4 duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between 5 this symbol represents the external ec_gtx_clk125 and does not follow the original signal naming convention. rx_clk rxd[3:0] t mrdxkl t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 27 ethernet: enhanced three-speed ethernet (etsec) figure 10 provides the ac test load for etsec. figure 10. etsec ac test load figure 11 shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 11. rgmii and rtbi ac timing and multiplexing diagrams output z 0 = 50 lvdd/2 r l = 50 gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 28 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec) 8.2.3 rmii ac timing specifications this section describes the rmii transmit and receive ac timing specifications. 8.2.3.1 rmii transmit ac timing specifications the rmii transmit ac timing specifications are in table 28 . figure 12 shows the rmii transmit ac timing diagram. figure 12. rmii transmit ac timing diagram table 28. rmii transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter symbol 1 min typical max unit ref_clk clock period t rmt 15.020.025.0 ns ref_clk duty cycle t rmth 35 50 65 % ref_clk peak-to-peak jitter t rmtj ? ? 250 ps rise time ref_clk (20%?80%) t rmtr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmtf 1.0 ? 2.0 ns ref_clk to rmii data txd[1:0], tx_en delay t rmtdx 2.0 ? 10.0 ns note: 1 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). ref_clk txd[1:0] t rmtdx t rmt t rmth t rmtr t rmtf tx_en tx_er
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 29 ethernet: enhanced three-speed ethernet (etsec) 8.2.3.2 rmii receive ac timing specifications table 29 shows the rmii receive ac timing specifications. figure 13 provides the ac test load for etsec. figure 13. etsec ac test load table 29. rmii receive ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typical max unit input low voltage at 3.3 lv dd v il ??0.8v input high voltage at 3.3 lv dd v ih 2.0 ? ? v ref_clk clock period t rmr 15.0 20.0 25.0 ns ref_clk duty cycle t rmrh 35 50 65 % ref_clk peak-to-peak jitter t rmrj ? ? 250 ps rise time ref_clk (20%?80%) t rmrr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmrf 1.0 ? 2.0 ns rxd[1:0], crs_dv, rx_er setup time to ref_clk rising edge t rmrdv 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk rising edge t rmrdx 2.0 ? ? ns note: 1 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). output z 0 = 50 lvdd/2 r l = 50
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 30 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec) figure 14 shows the rmii receive ac timing diagram. figure 14. rmii receive ac timing diagram 8.3 management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (management data input/output) and mdc (management data clock). figure 15 provides the ac test load for etsec. figure 15. etsec ac test load 8.3.1 mii management dc electrical characteristics the mdc and mdio are defined to operate at a supply voltage of 2.5 v or 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 30 and table 31 . table 30. mii management dc electrical characteristics when powered at 2.5 v parameter conditions symbol min max unit supply voltage (2.5 v) ? lv dd1 2.37 2.63 v output high voltage i oh = ?1.0 ma lv dd1 = min v oh 2.00 lv dd1 + 0.3 v output low voltage i ol = 1.0 ma lv dd1 = min v ol gnd ? 0.3 0.40 v input high voltage ? lv dd1 = min v ih 1.7 ? v input low voltage ? lv dd1 = min v il ?0.3 0.70 v input high current v in = lv dd1 i ih ?20 a input low current v in = lv dd1 i il ?15 ? a ref_clk rxd[1:0] t rmrdx t rmr t rmrh t rmrr t rmrf crs_dv rx_er t rmrdv valid data output z 0 = 50 lvdd/2 r l = 50
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 31 ethernet: enhanced three-speed ethernet (etsec) 8.3.2 mii management ac electrical specifications table 32 provides the mii management ac timing specifications. table 31. mii management dc electrical characteristics when powered at 3.3 v parameter conditions symbol min max unit supply voltage (3.3 v) ? lv dd1 3.135 3.465 v output high voltage i oh = ?1.0 ma lv dd1 = min v oh 2.10 lv dd1 +0.3 v output low voltage i ol = 1.0 ma lv dd1 = min v ol gnd 0.50 v input high voltage ? v ih 2.00 ? v input low voltage ? v il ?0.80v input high current lv dd1 = max v in 1 = 2.1 v i ih ?30 a input low current lv dd1 = max v in = 0.5 v i il ?600 ? a table 32. mii management ac timing specifications parameter symbol 1 min typical max unit notes mdc frequency f mdc 2.5 ? 8.3 mhz 2, 3 mdc period t mdc 80 ? 400 ns ? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio valid t mdkhdv 2 (t plb_clk 8) ? ns 5 mdc to mdio delay t mdkhdx 10 ? 2 (t plb_clk 8) ns 3, 5 mdio to mdc setup time t mddvkh 5??ns? mdio to mdc hold time t mddxkh 0??ns? mdc rise time t mdcr ??10ns4 mdc fall time t mdcf ??10ns4 note: 1 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2 this parameter is dependent on the system clock speed. (the maximum frequency is the maximum platform frequency divided by 64.) 3 this parameter is dependent on the system clock speed. (that is, for a system clock of 267 mhz, the maximum frequency is 8.3 mhz and the minimum frequency is 1.2 mhz; for a system clock of 375 mhz, the maximum frequency is 11.7 mhz and the minimum frequency is 1.7 mhz.) 4 guaranteed by design. 5 t plb_clk is the platform (csb) clock divided according to the sccr[tsec1cm].
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 32 freescale semiconductor usb figure 16 shows the mii management ac timing diagram. figure 16. mii management interface timing diagram 9usb this section provides the ac and dc electrical ch aracteristics for the usb dual-role controllers. 9.1 usb dc electrical characteristics table 33 provides the dc electrical characteristics for the usb interface at recommended ov dd = 3.3 v 165 mv. table 33. usb dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current i in ?30 a high-level output voltage, i oh = ?100 a v oh ov dd ? 0.2 ? v low-level output voltage, i ol = 100 a v ol ?0.2v note: the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 2 . mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output)
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 33 local bus 9.2 usb ac electrical specifications table 34 describes the general t iming parameters of the usb interface of the device. figure 17 and figure 18 provide the ac test load and signals for the usb, respectively. figure 17. usb ac test load figure 18. usb interface timing diagram 10 local bus this section describes the dc and ac electrical specifications for the local bus interface of the MPC8377E. table 34. usb general timing parameters (ulpi mode only) parameter symbol 1 min max unit usb clock cycle time t usck 15 ? ns input setup to usb clock?all inputs t usivkh 4?ns input hold to usb clock?all inputs t usixkh 1?ns usb clock to output valid?all outputs t uskhov ?7ns output hold from usb clock?all outputs t uskhox 2?ns output z 0 = 50 ovdd/2 r l = 50
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 34 freescale semiconductor local bus 10.1 local bus dc electrical characteristics table 35 and table 36 provides the dc electrical characteristics for the local bus interface. table 35. local bus dc electrical characteristics (lbv dd =3.3v) at recommended operating conditions with lbv dd = 3.3 v. parameter conditions symbol min max unit supply voltage 3.3 v ? lbv dd 3.135 3.465 v output high voltage i oh = ?4.0 ma lbv dd = min v oh 2.40 ? v output low voltage i ol = 4.0 ma lbv dd = min v ol ?0.50 v input high voltage ? ? v ih 2.0 lbv dd + 0.3 v input low voltage ? ? v il ?0.3 0.90 v input high current v in 1 = lbv dd i ih ?30 a input low current v in 1 = gnd i il ?30 ? a table 36. local bus dc electrical characteristics (lbv dd =2.5v) at recommended operating conditions with lbv dd = 2.5 v. parameter conditions symbol min max unit supply voltage 2.5 v ? lbv dd 2.37 2.73 v output high voltage i oh = ?1.0 ma lbv dd = min v oh 2.00 ? v output low voltage i ol = 1.0 ma lbv dd = min v ol ?0.40v input high voltage ? lbv dd = min v ih 1.7 lbv dd + 0.3 v input low voltage ? lbv dd = min v il ?0.3 0.70 v input high current v in 1 = lbv dd i ih ?20 a input low current v in 1 = gnd i il ?20 ? a table 37. local bus dc electrical characteristics (lbv dd =1.8v) at recommended operating conditions with lbv dd = 1.8 v. parameter conditions symbol min max unit supply voltage 1.8 v ? lbv dd 1.71 1.89 v output high voltage i oh = ?1.0 ma lbv dd = min v oh lbv dd ? 0.45 ? v output low voltage i ol = 1.0 ma lbv dd = min v ol ?0.45v input high voltage ? lbv dd = min v ih 0.65 lbv dd lbv dd + 0.3 v input low voltage ? lbv dd = min v il ?0.3 0.35 lbv dd v input high current v in 1 = lbv dd i ih ?10 a input low current v in 1 = gnd i il ?10 ? a
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 35 local bus 10.2 local bus ac electrical specifications table 38 describes the general timing parameters of the local bus interface of the device. table 38. local bus general timing parameters?pll enable mode parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 15 ns 2 input setup to local bus clock (except lupwait/lgta )t lbivkh 1.5 ? ns 3, 4 input hold from local bus clock t lbixkh 1.0 ? ns 3, 4 lupwait/lgta input setup to local bus clock t lbivkh1 1.5 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3?ns6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock to lale rise t lbkhlr ?4.5ns ? local bus clock to output valid (except lale) t lbkhov ?4.5ns 3 local bus clock to output high impedance for lad/ldp t lbkhoz ? 3.8 ns 3, 8 output hold from local bus clock for lad/ldp t lbkhox 1?ns3 note: 1 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2 all timings are in reference to rising edge of lsync_in at lbv dd /2 and the 0.4 lbv dd of the signal in question. 3 all signals are measured from lbv dd /2 of the rising/falling edge of lsync_in to 0.5 lbv dd of the signal in question. 4 input timings are measured at the pin. 5 t lbotot1 should be used when lbcr[ahd] is not set and the load on lale output pin is at least 10pf less than the load on lad output pins. 6 t lbotot2 should be used when lbcr[ahd] is set and the load on lale output pin is at least 10pf less than the load on lad output pins. 7 t lbotot3 should be used when lbcr[ahd] is set and the load on lale output pin equals to the load on lad output pins. 8 for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 36 freescale semiconductor local bus table 38 describes the general timing parameters of the local bus interface of the device. figure 19 provides the ac test load for the local bus. figure 19. local bus ac test load table 39. local bus general timing parameters?pll bypass mode parameter symbol 1 min max unit notes local bus cycle time t lbk 15 ? ns 2 input setup to local bus clock t lbivkh 7.0 ? ns 3, 4 input hold from local bus clock t lbixkh 1.0 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3.0 ? ns 6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock to output valid t lbkhov ?3.0ns 3 local bus clock to output high impedance for lad/ldp t lbkhoz ? 4.0 ns 3, 8 note: 1 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2 all timings are in reference to falling edge of lclk0 (for all outputs and for lgta and lupwait inputs) or rising edge of lclk0 (for all other inputs). 3 all signals are measured from lbv dd /2 of the rising/falling edge of lclk0 to 0.4 lbv dd of the signal in question for 3.3-v signaling levels. 4 input timings are measured at the pin. 5 t lbotot1 should be used when lbcr[ahd] is not set and the load on lale output pin is at least 10pf less than the load on lad output pins. 6 t lbotot2 should be used when lbcr[ahd] is set and the load on lale output pin is at least 10pf less than the load on lad output pins. 7 t lbotot3 should be used when lbcr[ahd] is set and the load on lale output pin equals to the load on lad output pins. 8 for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. output z 0 = 50 ovdd/2 r l = 50
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 37 local bus figure 20 through figure 25 show the local bus signals. figure 20. local bus signals, non-special signals only (pll enable mode) output signals: la[27:31]/lbctl/lbcke/loe lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh t lbivkh t lbkhox t lbkhoz t lbkhlr t lbotot t lbkhox t lbkhov t lbkhox t lbkhoz t lbkhov t lbkhov input signal: lgta t lbixkh t lbivkh
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 38 freescale semiconductor local bus figure 21. local bus signals, non-special signals only (pll bypass mode) lclk[n] input signals: lad[0:15] t lbixkh t lbivkh input signal: lgta t lbixkh t lbivkh output signals: la[27:31]/lbctl/lbcke/loe lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov t lbkhov output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbkhoz t lbkhlr t lbotot t lbkhoz t lbkhov
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 39 local bus figure 22. local bus si gnals, gpcm/upm signals for lccr[clkdiv] = 2 (pll enable mode) lsync_in upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:1]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe [0:3] t lbkhov t lbkhov output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] t lbkhox t lbkhov t lbkhov t lbkhox t lbkhoz t lbkhox t lbkhoz t lbkhox
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 40 freescale semiconductor local bus figure 23. local bus si gnals, gpcm/upm signals for lccr[clkdiv] = 2 (pll bypass mode) lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t1 t3 input signals: lad[0:31]/ldp[0:3] gpcm mode output signals: lcs [0:7]/lwe [0:3] t lbkhov t lbkhoz upm mode output signals: lcs [0:7]/lbs [0:1]/lgpl[0:5] t lbkhov output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] t lbkhoz t lbkhoz t lbkhov t lbkhov
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 41 local bus figure 24. local bus si gnals, gpcm/upm signals for lccr[clkdiv] = 4 (pll enable mode) lsync_in upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t1 t3 gpcm mode output signals: lcs [0:7]/lwe [0:3] t lbkhov t lbkhoz t2 t4 input signals: lad[0:31] upm mode output signals: lcs [0:7]/lbs [0:1]/lgpl[0:5] t lbkhov output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] t lbkhox t lbkhoz t lbkhoz t lbkhox t lbkhov t lbkhov t lbkhox
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 42 freescale semiconductor enhanced secure digital host controller (esdhc) figure 25. local bus si gnals, gpcm/upm signals for lccr[clkdiv] = 4 (pll bypass mode) 11 enhanced secure digital host controller (esdhc) this section describes the dc and ac electrical specifications for the esdhc (sd/mmc) interface of the MPC8377E. the esdhc controller always uses the falling edge of the sd_clk in order to drive the sd_dat[0:3]/cmd as outputs and sample the sd_dat[0:3] as inputs. this behavior is true for both full- and high-speed modes. note that this is a non-standard imp lementation, as the sd card specification assumes that in high-speed mode, that data will be driven at the rising edge of the clock. lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t1 t3 gpcm mode output signals: lcs [0:7]/lwe [0:3] t lbkhov t lbkhoz t2 t4 input signals: lad[0:31] upm mode output signals: lcs [0:7]/lbs [0:1]/lgpl[0:5] t lbkhov output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] t lbkhoz t lbkhoz t lbkhov t lbkhov
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 43 enhanced secure digital host controller (esdhc) due to the special implementation of the esdhc, there are constraints regarding the clock and data signals propagation delay on the user board. the constraints are for minimum and maximum delays, as well as skew between the clk and dat/cmd signals. in full speed mode, there is no need to add special de lay on the data or clock signals. the user should make sure to meet the timing requirements as described further within this document. if the system is designed to support both high-speed and full-speed cards, the high-speed constraints should be fulfilled. if the systems is designed to operate up to 25 mhz only, full-speed mode is recommended. 11.1 esdhc dc electrical characteristics table 40 provides the dc electrical characteristics for the esdhc (sd/mmc) interface of the device. 11.2 esdhc ac timing specifications (full-speed mode) this section describes the ac electrical specifications for the esdhc (sd/mmc) interface of the device. table 41 provides the esdhc ac timing specifications for full-speed mode as defined in figure 27 and figure 28 . table 40. esdhc interface dc electrical characteristics parameter symbol condition min max unit input high voltage v ih ? 0.625 ov dd ov dd +0.3 v input low voltage v il ? ?0.3 0.25 ov dd v input current i in ??30 a output high voltage v oh i oh = ?100 ua, at ov dd (min) 0.75 ov dd ?v output low voltage v ol i ol = +100 ua, at ov dd (min) ? 0.125 ov dd v table 41. esdhc ac timing specifications for full-speed mode at recommended operating conditions ov dd = 3.3 v 165 mv. parameter symbol 1 min max unit notes sd_clk clock frequency?full speed mode f sfsck 025mhz? sd_clk clock cycle t sfsck 40 ? ns ? sd_clk clock frequency?identification mode f sidck 0400khz? sd_clk clock low time t sfsckl 15 ? ns 2 sd_clk clock high time t sfsckh 15 ? ns 2 sd_clk clock rise and fall times t sfsckr / t sfsckf ?5ns2 input setup times: sd_cmd, sd_datx, sd_cd to sd_clk t sfsivkh 5?ns2
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 44 freescale semiconductor enhanced secure digital host controller (esdhc) figure 26 provides the esdhc clock input timing diagram. figure 26. esdhc clock input timing diagram input hold times: sd_cmd, sd_dat x , sd_cd to sd_clk t sfsixkh 0?ns2 sd_clk delay within device t int_clk_dly 1.5 ? ns 4 output valid: sd_clk to sd_cmd, sd_dat x valid t sfskhov ?4ns2 output hold: sd_clk to sd_cmd, sd_dat x valid t sfskhox 0??? sd card input setup t isu 5?ns3 sd card input hold t ih 5?ns3 sd card output valid t odly ?14ns3 sd card output hold t oh 0?ns3 notes: 1 the symbols used for timing specifications herein follow the pattern of t (first three letters of functional block)(signal)(state) (reference)(state) for inputs and t (first three letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t sfsixkh symbolizes esdhc full mode speed device timing (sfs) input (i) to go invalid (x) with respect to the clock reference (k) going to high (h). also t sfskhov symbolizes esdhc full speed timing (sfs) for the clock reference (k) to go high (h), with respect to the output (o) going valid (v) or data output valid time. note that, in general, the clock reference symbol representation i s based on five letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2 measured at capacitive load of 40 pf. 3 for reference only, according to the sd card specifications. 4 average, for reference only. table 41. esdhc ac timing specifications for full-speed mode (continued) at recommended operating conditions ov dd = 3.3 v 165 mv. parameter symbol 1 min max unit notes esdhc t sfsckr external clock vm vm vm t sfsck t sfsckf vm = midpoint voltage (ov dd /2) operational mode t sfsckl t sfsckh
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 45 enhanced secure digital host controller (esdhc) 11.2.1 full-speed output path (write) figure 27 provides the data and command output timing diagram. figure 27. full speed output path 11.2.1.1 full-speed write meeting setup (maximum delay) the following equations show how to calculate the allowed skew range between the sd_clk and sd_dat/cmd signals on the pcb. no clock delay: t sfskhov + t data_delay + t isu < t sfsckl with clock delay: t sfskhov + t data_delay + t isu < t sfsckl + t clk_delay t data_delay + t sfsckl < t sfsck + t clk_delay ? t isu ? t sfskhov this means that data can be delayed vers us clock up to 11 ns in ideal case of t sfsckl =20ns: t data_delay + 20 < 40 + t clk_delay ? 5 ? 4 t data_delay < 11 + t clk_delay 11.2.1.2 full-speed write meeting hold (minimum delay) the following equations show how to calculate the allowed skew range between the sd_clk and sd_dat/cmd signals on the pcb. t clk_delay < t sfsckl + t sfskhox + t data_delay ? t ih t clk_delay + t ih ? t sfskhox < t sfsckl + t data_delay input at the MPC8377E pins sd clk at the MPC8377E pin output valid time: t sfskhov output hold time: t sfskhox t ih (5 ns) t clk_delay sd clk at driving edge sampling edge the card pin t isu (5 ns) t data_delay t sfsckl t sfsck (clock cycle) output from the MPC8377E pins
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 46 freescale semiconductor enhanced secure digital host controller (esdhc) this means that clock can be dela yed versus data up to 15 ns (exter nal delay line) in ideal case of t sfsclkl =20ns: t clk_delay + 5 ? 0 < 20 + t data_delay t clk_delay < 15 + t data_delay 11.2.1.3 full-speed write combined formula the following equation is the combined formula to calculate the allowed skew range between the sd_clk and sd_dat/cmd signals on the pcb. t clk_delay + t ih ? t sfskhox < t sfsckl + t data_delay < t sfsck + t clk_delay ? t isu ? t sfskhov 11.2.2 full-speed input path (read) figure 28 provides the data and command input timing diagram. figure 28. full speed input path 11.2.2.1 full-speed read meeting setup (maximum delay) the following equations show how to calculate th e allowed combined propagation delay range of the sd_clk and sd_dat/cmd signals on the pcb. t clk_delay + t data_delay + t odly + t sfsivkh < t sfsck t clk_delay + t data_delay < t sfsck ? t odly ? t sfsivkh ? t int_clk_dly 11.2.2.2 full-speed read meeting hold (minimum delay) there is no minimum delay constraint due to the full clock cycle between the driving and sampling of data. t clk_delay + t oh + t data_delay > t sfsixkh t clk_delay output from the sd clk at the card pin sd card pins t sfsivkh t sfsixkh driving edge sampling edge t oh t data_delay t odly t sfsck (clock cycle) (MPC8377E input hold) sd clk at the MPC8377E pin input at the MPC8377E pins
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 47 enhanced secure digital host controller (esdhc) this means that data + clock delay must be greater than ?2 ns. this is always fulfilled. 11.3 esdhc ac timing specifications (high-speed mode) table 42 provides the esdhc ac timing specifications for high-speed mode as defined in figure 30 and figure 31 . table 42. esdhc ac timing specifications for high-speed mode at recommended operating conditions ov dd = 3.3 v 165 mv. parameter symbol 1 min max unit notes sd_clk clock frequency?high speed mode f shsck 050mhz? sd_clk clock cycle t sfsck 20 ? ns ? sd_clk clock frequency?identification mode f sidck 0400khz? sd_clk clock low time t shsckl 7?ns2 sd_clk clock high time t shsckh 7?ns2 sd_clk clock rise and fall times t shsckr/ t shsckf ?3ns2 input setup times: sd_cmd, sd_datx, sd_cd to sd_clk t shsivkh 5?ns2 input hold times: sd_cmd, sd_datx, sd_cd to sd_clk t shsixkh 0?ns2 output delay time: sd_clk to sd_cmd, sd_datx valid t shskhov ?4ns2 output hold time: sd_clk to sd_cmd, sd_datx invalid t shskhox 0?ns2 sd_clk delay within device t int_clk_dly 1.5 ? ns 4 sd card input setup t isu 6?ns3 sd card input hold t ih 2?ns3 sd card output valid t odly ?14ns3 sd card output hold t oh 2.5 ? ns 3 note: 1 the symbols used for timing specifications herein follow the pattern of t (first three letters of functional block)(signal)(state) (reference)(state) for inputs and t (first three letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t sfsixkh symbolizes esdhc full mode speed device timing (sfs) input (i) to go invalid (x) with respect to the clock reference (k) going to high (h). also t sfskhov symbolizes esdhc full speed timing (sfs) for the clock reference (k) to go high (h), with respect to the output (o) going valid (v) or data output valid time. note that, in general, the clock reference symbol representation i s based on five letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2 measured at capacitive load of 40 pf. 3 for reference only, according to the sd card specifications. 4 average, for reference only.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 48 freescale semiconductor enhanced secure digital host controller (esdhc) figure 29 provides the esdhc clock input timing diagram. figure 29. esdhc clock input timing diagram 11.3.1 high-speed output path (write) figure 30 provides the data and command output timing diagram. figure 30. high speed output path 11.3.1.1 high-speed write meeting setup (maximum delay) the following equations show how to calculate the allowed skew range between the sd_clk and sd_dat/cmd signals on the pcb. zero clock delay: t shskhov + t data_delay + t isu < t shsckl with clock delay: t shskhov + t data_delay + t isu < t shsckl + t clk_delay t data_delay ? t clk_delay < t shsckl ? t isu ? t shskhov esdhc t shsckr external clock vm vm vm t shsck t shsckf vm = midpoint voltage (ovdd/2) operational mode t shsck l t shsckh output valid time: t shskhov output hold time: t shskhox t ih (2 ns) t clk_delay input at the sd clk at driving edge sampling edge the card pin sd card pins t isu (6 ns) t data_delay t shsckl t shsck (clock cycle) sd clk at the MPC8377E pin output from the MPC8377E pins
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 49 enhanced secure digital host controller (esdhc) this means that data delay shoul d be equal or less than the clock delay in the ideal case where t shsclkl =10ns: t data_delay ? t clk_delay < 10 ? 6 ? 4 t data_delay ? t clk_delay < 0 11.3.1.2 high-speed write meeting hold (minimum delay) the following equations show how to calculate the allowed skew range between the sd_clk and sd_dat/cmd signals on the pcb. t clk_delay < t shsckl + t shskhox + t data_delay ? t ih t clk_delay ? t data_delay < t shsckl + t shskhox ? t ih this means that clock can be dela yed versus data up to 8 ns (exter nal delay line) in ideal case of t shsclkl =10ns: t clk_delay ? t data_delay < 10 + 0 ? 2 t clk_delay ? t data_delay < 8 11.3.2 high-speed input path (read) figure 31 provides the data and command input timing diagram. figure 31. high speed input path for the input path, the device esdhc expects to samp le the data 1.5 internal clock cycles after it was driven by the sd card. since in this mode the sd card drives the data at the rising edge of the clock, a sufficient delay to the clock and th e data must exist to ensure it will not be sampled at the wrong internal clock falling edge. note that the internal clock which is guaranteed to be 50% duty cycle is used to sample the data, and therefore used in the equations. t clk_delay output from the sd clk at the card pin sd card pins t shsivkh driving edge sampling edge t oh t data_delay t odly t shsck (clock cycle) 1/2 cycle t shsixkh right edge wrong edge (MPC8377E input hold) (MPC8377E input setup) input at the MPC8377E pins sd clk at the MPC8377E pin
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 50 freescale semiconductor jtag 11.3.2.1 high-speed read meeting setup (maximum delay) the following equations show how to calculate th e allowed combined propagation delay range of the sd_clk and sd_dat/cmd signals on the pcb. t clk_delay + t data_delay + t odly + t shsivkh < 1.5 t shsck t clk_delay + t data_delay < 1.5 t shsck ? t odly ? t shsivkh this means that data + clock delay can be up to 11 ns for a 20 ns clock cycle: t clk_delay + t data_delay < 30 ? 14 ? 5 t clk_delay + t data_delay < 11 11.3.2.2 high-speed read meeting hold (minimum delay) the following equations show how to calculate th e allowed combined propagation delay range of the sd_clk and sd_dat/cmd signals on the pcb. 0.5 t shsck < t clk_delay + t data_delay + t oh ? t shsixkh + t int_clk_dly 0.5 t shsck ? t oh + t shsixkh ? t int_clk_dly < t clk_delay + t data_delay this means that data + clock delay must be greater than ~6 ns for a 20 ns clock cycle: 10 ? 2.5 + (-1.5) < t clk_delay + t data_delay 6 < t clk_delay + t data_delay 11.3.2.3 high-speed read combined formula the following equation is the combined formula to cal culate the propagation delay range of the sd_clk and sd_dat/cmd signals on the pcb. 0.5 t shsck ? t oh + t shsixkh < t clk_delay + t data_delay < 1.5 t shsck ? t odly ? t shsivkh 12 jtag this section describes the dc and ac electrical sp ecifications for the ieee 1149.1 (jtag) interface of the MPC8377E. 12.1 jtag dc electrical characteristics table 43 provides the dc electrical characteristics fo r the ieee 1149.1 (jtag) interface of the MPC8377E. table 43. jtag interface dc electrical characteristics parameter symbol condition min max unit input high voltage v ih ?2.5ov dd +0.3 v input low voltage v il ??0.30.8v input current i in ??30 a
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 51 jtag 12.2 jtag ac timing specifications this section describes the ac electrical specifications for the ieee 1149.1 (jtag) interface of the device. table 44 provides the jtag ac timing specifications as defined in figure 33 through figure 36 . output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 44. jtag ac timing specifications (independent of clkin) 1 parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 033.3mhz? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns ? jtag external clock rise and fall times t jtgr & t jtgf 02ns? trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 2 2 11 11 ns ? output hold times: boundary-scan data tdo t jtkldx t jtklox 2 2 ? ? ns ? table 43. jtag interface dc electrical characteristics (continued) parameter symbol condition min max unit
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 52 freescale semiconductor jtag figure 32 provides the ac test load for tdo and the boundary-scan outputs of the device. figure 32. ac test load for the jtag interface figure 33 provides the jtag clock input timing diagram. figure 33. jtag clock input timing diagram figure 34 provides the trst timing diagram. figure 34. trst timing diagram jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 2 2 19 9 ns 5 notes: 1 all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50 load (see figure 17 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3 trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4 non-jtag signal input timing with respect to t tclk . 5 non-jtag signal output timing with respect to t tclk . table 44. jtag ac timing specifications (independent of clkin) 1 (continued) parameter symbol 2 min max unit notes output z 0 = 50 ovdd/2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ovdd/2) trst vm = midpoint voltage (ovdd/2) vm vm t trst
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 53 jtag figure 35 provides the boundary-scan timing diagram. figure 35. boundary-scan timing diagram figure 36 provides the test access port timing diagram. figure 36. test access port timing diagram vm = midpoint voltage (ovdd/2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid vm = midpoint voltage (ovdd/2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 54 freescale semiconductor i 2 c 13 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the MPC8377E. 13.1 i 2 c dc electrical characteristics table 45 provides the dc electrical characteristics for the i 2 c interface of the MPC8377E. 13.2 i 2 c ac electrical specifications table 46 provides the ac timing parameters for the i 2 c interface of the device. table 45. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 165 mv. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd + 0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00.2 ov dd v1 output fall time from v ih (min) to v il (max) with a bus capacitance from 10 to 400 pf t i2klkv 20 + 0.1 c b 250 ns 2 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns3 capacitance for each i/o pin c i ?10pf? input current (0 v v in ov dd ) i in ? 30 a4 note: 1 output voltage (open drain or open collector) condition = 3 ma sink current. 2 c b = capacitance of one bus line in pf. 3 refer to the mpc8379e powerquicc ii pro integrated host processor reference manual for information on the digital filter used. 4 i/o pins will obstruct the sda and scl lines if ov dd is switched off. table 46. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see table 45 ). parameter symbol 1 min max unit notes scl clock frequency f i2c 0 400 khz ? low period of the scl clock t i2cl 1.3 ? s? high period of the scl clock t i2ch 0.6 ? s? setup time for a repeated start condition t i2svkh 0.6 ? s? hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s? data setup time t i2dvkh 100 ? ns ?
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 55 i 2 c figure 37 provides the ac test load for the i 2 c. figure 37. i 2 c ac test load figure 38 shows the ac timing diagram for the i 2 c bus. figure 38. i 2 c bus ac timing diagram data hold time cbus compatible masters i 2 c bus devices t i2dxkl ? 0 ? 0.9 s2, 3 setup time for stop condition t i2pvkh 0.6 ? s? bus free time between a stop and start condition t i2khdx 1.3 ? s? noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v? noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v? note: 1 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). 2 MPC8377E provides a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 3 the maximum t i2dvkh has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. table 46. i 2 c ac electrical specifications (continued) all values refer to v ih (min) and v il (max) levels (see table 45 ). parameter symbol 1 min max unit notes output z 0 = 50 ovdd/2 r l = 50 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 56 freescale semiconductor pci 14 pci this section describes the dc and ac electrical specifications for the pci bus of the MPC8377E. 14.1 pci dc electrical characteristics table 47 provides the dc electrical characteristics for the pci interface of the device. the dc characteristics of the poreset signal, which can be used as pci rst in applications where the device is a pci agent, deviates from the standard pci levels. 14.2 pci ac electrical specifications this section describes the general ac timing parameters of the pci bus of the device. note that the pci_clk/pci_sync_in or clkin signal is used as the pci input clock depending on whether the MPC8377E is configured as a host or agent device. clkin is used when the device is in host mode. table 48 shows the pci ac timing specifications at 66 mhz. . table 47. pci dc electrical characteristics parameter condition symbol min max unit high-level input voltage v out v oh (min) or v ih 0.5 ov dd ov dd + 0.5 v low-level input voltage v out v ol (max) v il ?0.5 0.3 ov dd v high-level output voltage i oh = ?500 av oh 0.9 ov dd ?v low-level output voltage i ol = 1500 av ol ?0.1 ov dd v input current 0 v v in ov dd i in ? 30 a note: ? the symbol v in , in this case, represents the ov in symbol referenced in ta ble 2 . table 48. pci ac timing specifications at 66 mhz pci_sync_in clock input levels are with next levels: vil = 0.1 ov dd , vih = 0.7 ov dd . parameter symbol 1 min max unit notes clock to output valid t pckhov ?6.0ns2 output hold from clock t pckhox 1?ns2 clock to output high impedance t pckhoz ?14ns2, 3 input setup to clock t pcivkh 3.0 ? ns 2, 4
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 57 pci table 49 shows the pci ac timing specifications at 33 mhz. input hold from clock t pcixkh 0.25 ? ns 2, 4, 6 output clock skew t pckosk ?0.5ns5 notes: 1 note that the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2 see the timing measurement conditions in the pci 2.3 local bus specifications . 3 for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4 input timings are measured at the pin. 5 pci specifications allows 1 ns skew for 66 mhz but includes the total allowed skew, board, connectors, etc. 6 value does not comply with the pci 2.3 local bus specifications . table 49. pci ac timing specifications at 33 mhz pci_sync_in clock input levels are with next levels: vil = 0.1 ov dd , v ih = 0.7 ov dd . parameter symbol 1 min max unit notes clock to output valid t pckhov ?11ns2 output hold from clock t pckhox 2?ns2 clock to output high impedance t pckhoz ?14ns2, 3 input setup to clock t pcivkh 3.0 ? ns 2, 4 input hold from clock t pcixkh 0.25 ? ns 2, 4, 6 output clock skew t pckosk ?0.5ns5 note: 1 note that the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2 see the timing measurement conditions in the pci 2.3 local bus specifications . 3 for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4 input timings are measured at the pin. 5 pci specifications allows 2 ns skew for 33 mhz but includes the total allowed skew, board, connectors, etc. 6 value does not comply with the pci 2.3 local bus specifications . table 48. pci ac timing specifications at 66 mhz (continued) pci_sync_in clock input levels are with next levels: vil = 0.1 ov dd , vih = 0.7 ov dd . parameter symbol 1 min max unit notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 58 freescale semiconductor pci express figure 39 provides the ac test load for pci. figure 39. pci ac test load figure 40 shows the pci input ac timing conditions. figure 40. pci input ac timing measurement conditions figure 41 shows the pci output ac timing conditions. figure 41. pci output ac timing measurement condition 15 pci express this section describes the dc and ac electrical specifications for the pci express bus. 15.1 dc requirements for pci express sd_ref_clk and sd_ref_clk for more information see section 21, ?high-speed serial interfaces (hssi).? output z 0 = 50 ovdd/2 r l = 50 t pcivkh clk input t pcixkh clk output delay t pckhov high-impedance t pckhoz output t pckhox
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 59 pci express 15.2 ac requirements for pci express serdes clocks table 50 lists the pci express serdes clock ac requirements. 15.3 clocking dependencies the ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. this is specified to allow bit rate clock sources with a 300 ppm tolerance. 15.4 physical layer specifications following is a summary of the specifications for the physical layer of pci express on this device. for further details as well as the specifications of the transport and data link layer please use the pci express base specification , rev. 1.0a. note the voltage levels of the transmitter and the receiver depend on the serdes control registers which should be programmed at the recommended values for pci express protocol (that is, l1_ n v dd = 1.0 v). table 50. sd_ref_clk and sd_ref_clk ac requirements parameter symbol min typical max unit notes refclk cycle time t ref ?10?ns? refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles. t refcj ? ? 100 ps ? refclk phase jitter peak-to-peak. deviation in edge location with respect to mean edge location. t refpj ?50 ? +50 ps ? sd_ref_clk/_b cycle to cycle clock jitter (period jitter) t ckcj ? ? 100 ps ? sd_ref_clk/_b phase jitter peak-to-peak. deviation in edge location with respect to mean edge location. t ckpj ?50 ? +50 ps 2, 3 note: 1 all options provide serial interface bit rate of 1.5 and 3.0 gbps. 2 in a frequency band from 150 khz to 15 mhz, at ber of 10 -12 . 3 total peak-to-peak deterministic jitter ?j d ? should be less than or equal to 50 ps.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 60 freescale semiconductor pci express 15.4.1 differential transmitter (tx) output table 51 defines the specifications for the differential output at all transmitters. the parameters are specified at the component pins. table 51. differential transmitter (tx) output specifications parameter conditions symbol min typical max units notes unit interval each u petx is 400 ps 300 ppm. u petx does not account for spread spectrum clock dictated variations. ui 399.88 400 400.12 ps 1 differential peak-to-peak output voltage v pedpptx = 2 |v tx-d+ ? v tx-d- | v tx-diffp-p 0.8 ? 1.2 v 2 de-emphasized differential output voltage (ratio) ratio of the v pedpptx of the second and following bits after a transition divided by the v pedpptx of the first bit after a transition. v tx-de-ratio ?3.0 ?3.5 ?4.0 db 2 minimum tx eye width the maximum transmitter jitter can be derived as t tx-max-jitter = 1 ? u peewtx = 0.3 ui. t tx-eye 0.70 ? ? ui 2, 3 maximum time between the jitter median and maximum deviation from the median jitter is defined as the measurement variation of the crossing points (v pedpptx = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. t tx-eye-median-to- max-jitter ? ? 0.15 ui 2, 3 d+/d? tx output rise/fall time ?t tx-rise , t tx-fall 0.125 ? ? ui 2, 5 rms ac peak common mode output voltage v peacpcmtx = rms(|v txd+ ? v txd- |/2 ? v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ ? v tx-d- |/2 v tx-cm-acp ??20mv2 absolute delta of dc common mode voltage during lo and electrical idle |v tx-cm-dc (during lo) ? v tx-cm-idle-dc (during electrical idle) |<=100 mv v tx-cm-dc = dc (avg) of |v tx-d+ ? v tx-d- |/2 [lo] v tx-cm-idle-dc = dc (avg) of |v tx-d+ ? v tx-d- |/2 [electrical idle] v tx-cm-dc- active- idle-delta 0?100mv2
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 61 pci express absolute delta of dc common mode between d+ and d? |v tx-cm-dc-d+ ? v tx-cm-dc-d- | 25 mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d- = dc (avg) of |v tx-d- | v tx-cm-dc-line- delta 0?25mv2 electrical idle differential peak output voltage v peeidptx = |v tx-idle-d+ -v tx-idle-d- | 20 mv v tx-idle-diffp 0?20mv2 amount of voltage change allowed during receiver detection the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. v tx-rcv-detect ?xpadv dd /2 600 mv 6 tx dc common mode voltage the allowed dc common mode voltage under any conditions. v tx-dc-cm 0xpadv dd /2 ? v 6 tx short circuit current limit the total current the transmitter can provide when shorted to its ground i tx-short ??90ma? minimum time spent in electrical idle minimum time a transmitter must be in electrical idle. utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set. t tx-idle-min 50 ? ? ui ? maximum time to transition to a valid electrical idle after sending an electrical idle ordered set after sending an electrical idle ordered set, the transmitter must meet all electrical idle specifications within this time. this is considered a debounce time for the transmitter to meet electrical idle after transitioning from lo. t tx-idle-set-to-idle ??20ui? maximum time to transition to valid tx specifications after leaving an electrical idle condition maximum time to meet all tx specifications when transitioning from electrical idle to sending differential data. this is considered a debounce time for the tx to meet all tx specifications after leaving electrical idle t tx-idle-to-diff-data ??20ui? differential return loss measured over 50 mhz to 1.25 ghz. rl tx-diff 12 ? ? db 4 table 51. differential transmitter (tx) output specifications (continued) parameter conditions symbol min typical max units notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 62 freescale semiconductor pci express 15.4.2 transmitter compliance eye diagrams the tx eye diagram in figure 42 is specified using the passive compliance/test measurement load (see figure 44 ) in place of any real pci express interconnect + rx component. there are two eye diagrams that must be met for the transmitter. both diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diag rams differ in voltage depending on whether it is a common mode return loss measured over 50 mhz to 1.25 ghz. rl tx-cm 6??db4 dc differential tx impedance tx dc differential mode low impedance z tx-diff-dc 80 100 120 ? transmitter dc impedance required tx d+ as well as d? dc impedance during all states z tx-dc 40 ? ? ? lane-to-lane output skew static skew between any two transmitter lanes within a single link l tx-skew ? ? 500 + 2ui ps ? ac coupling capacitor all transmitters should be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. c tx 75 ? 200 nf ? crosslink random timeout this random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. t crosslink 0?1ms7 note: 1 no test load is necessarily associated with this value. 2 specified at the measurement point into a timing and voltage compliance test load as shown in figure 44 and measured over any 250 consecutive tx uis. (also refer to the transmitter compliance eye diagram shown in figure 42 .) 3 a t tx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of t tx-jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as oppose d to the averaged time value. 4 the transmitter input impedance will result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes, see figure 44 ). note that the series capacitors, c tx , is optional for the return loss measurement. 5 measured between 20%?80% at transmitter package pins into a test load as shown in figure 44 for both v tx-d+ and v tx-d- . 6 see section 4.3.1.8 of the pci express base specifications , rev 1.0a. 7 see section 4.2.6.3 of the pci express base specifications , rev 1.0a. table 51. differential transmitter (tx) output specifications (continued) parameter conditions symbol min typical max units notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 63 pci express transition bit or a de-emphasized bit. the exact reduced voltage level of the de-emphasized bit is always relative to the transition bit. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note it is recommended that the recovered tx ui be calculated using all edges in the 3500 consecutive ui interval with a fit algorithm using a minimization merit function (that is, least squa res and median deviation fits). figure 42. minimum transmitter timing and voltage output compliance specifications 15.4.3 differential receiver (rx) input specifications table 52 defines the specifications for the differential input at all receivers. the parameters are specified at the component pins. table 52. differential receiver (rx) input specifications parameter comments symbol min typical max units notes unit interval each u perx is 400 ps 300 ppm. u perx does not account for spread spectrum clock dictated variations. ui 399.88 400 400.12 ps 1 differential peak-to-peak output voltage v pedpprx = 2 |v rx-d+ ? v rx-d- | v rx-diffp-p 0.175 ? 1.200 v 2 [de-emphasized bit] 566 mv (3 db) >= v tx-diffp-p-min >= 505 mv (4 db) [transition bit] v tx-diffp-p-min = 800 mv [transition bit] v tx-diffp-p-min = 800 mv 0.7 ui = ui ? 0.3 ui(j tx-total-max ) v tx-diff = 0 mv (d+ d? crossing point) v tx-diff = 0 mv (d+ d? crossing point)
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 64 freescale semiconductor pci express minimum receiver eye width the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter = 1 ? u peewrx = 0.6 ui. t rx-eye 0.4??ui2, 3 maximum time between the jitter median and maximum deviation from the median. jitter is defined as the measurement variation of the crossing points (v pedpprx = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. t rx-eye-median-to -max-jitter ? ? 0.3 ui 2, 3, 7 ac peak common mode input voltage v peacpcmrx = |v rxd+ ? v rxd- |/2 ? v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ ? v rx-d- |/2 v rx-cm-acp ? ? 150 mv 2 differential return loss measured over 50 mhz to 1.25 ghz with the d+ and d? lines biased at +300 mv and ?300 mv, respectively. rl rx-diff 10 ? ? db 4 common mode return loss measured over 50 mhz to 1.25 ghz with the d+ and d? lines biased at 0 v. rl rx-cm 6??db4 dc differential input impedance rx dc differential mode impedance. z rx-diff-dc 80 100 120 5 dc input impedance required rx d+ as well as d- dc impedance (50 20% tolerance). z rx-dc 40 50 60 2, 5 powered down dc input impedance required rx d+ as well as d? dc impedance when the receiver terminations do not have power. z rx-high-imp-dc 200 k ? ? 6 electrical idle detect threshold v peeidt = 2 |v rx-d+ -v rx-d- | measured at the package pins of the receiver v rx-idle-det-diff p-p 65 ? 175 mv ? table 52. differential receiver (rx) input specifications (continued) parameter comments symbol min typical max units notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 65 pci express 15.5 receiver compliance eye diagrams the rx eye diagram in figure 43 is specified using the passive compliance/test measurement load (see figure 44 ) in place of any real pci express rx component. in general, the minimum receiver eye diagram measured with the compliance/test measurement load (see figure 44 ) is larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real pci express component. the degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon unexpected electrical idle enter detect threshold integration time an unexpected electrical idle (vrx-diffp-p < vrx-idle-det-diffp-p) must be recognized no longer than trx-idle-det-diff-entertime to signal an unexpected idle condition. t rx-idle-det-diff- entertime ??10ms? total skew skew across all lanes on a link. this includes variation in the length of skp ordered set (e.g. com and one to five skp symbols) at the rx as well as any delay differences arising from the interconnect itself. l rx-skew ? ? 20 ns ? note: 1 no test load is necessarily associated with this value. 2 specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 44 should be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram shown in figure 43 ). if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3 a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the trx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4 the receiver input impedance will result in a differential return loss greater than or equal to 10 db with the d+ line biased t o 300 mv and the d? line biased to ?300 mv and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements for is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes, see figure 44 ). note that the series capacitors, c tx , is optional for the return loss measurement. 5 impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 6 the rx dc common mode impedance that exists when no power is present or fundamental reset is asserted. this helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. 7 it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algorit hm using a minimization merit function. least squares and median deviation fits have worked well with experimental and simulated data. table 52. differential receiver (rx) input specifications (continued) parameter comments symbol min typical max units notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 66 freescale semiconductor pci express parasitic characteristics that cause the real pci express component to vary in impedance from the compliance/test measurement load. the input receiver eye diagram is implementation specific and is not specified. rx component designer should provide add itional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in figure 43 ) expected at the input receiver based on an adequate combination of system simulations and the re turn loss measured looking into the rx package and silicon. the rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note the reference impedance for return loss measurements is 50. to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50. probes?see figure 44 ). note that the series capacitors, c peacctx , are optional for the return loss measurement. figure 43. minimum receiver eye timing and voltage compliance specification v rx-diffp-p-min > 175 mv 0.4 ui = t rx-eye-min v rx-diff = 0 mv (d+ d? crossing point) v rx-diff = 0 mv (d+ d? crossing point)
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 67 serial ata (sata) 15.5.1 compliance test and measurement load the ac timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in figure 44 . note the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from d+ and d? not being exac tly matched in length at the package pin boundary. if the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the d+ and d? package pins. figure 44. compliance test/measurement load 16 serial ata (sata) this section describes the dc and ac electrical specifications for the serial ata (sata) of the MPC8377E. note that the external cabled applications or long backplane applications (gen1x and gen2x) are not supported. 16.1 requirements for sata ref_clk the reference clock is a single ended input clock required for the sata interface operation. the ac requirements for the sata reference clock are listed in the table 53 . table 53. sata reference clock input requirements parameter condition symbol min typical max unit notes sd_ref_clk/ sd_ref_clk frequency range ?t clk_ref ? 100/125/150 ? mhz 1 sd_ref_clk/ sd_ref_clk clock frequency tolerance ?t clk_tol ?350 0 +350 ppm ? sd_ref_clk/ sd_ref_clk reference clock duty cycle measured at 1.6v t clk_duty 40 50 60 % ? tx silicon + package r = 50 r = 50 c = c tx c = c tx d+ package pin d? package pin
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 68 freescale semiconductor serial ata (sata) figure 45 shows the sata reference clock timing waveform. figure 45. sata reference clock timing waveform 16.2 transmitter (tx) output characteristics this section discusses the gen1i/1.5g and gen2i/3g transmitter output characteristics for the sata interface. 16.2.1 gen1i/1.5g transmitter specifications table 54 provides the dc differential transmitter output dc characteristics for the sata interface at gen1i or 1.5 gbits/s transmission. sd_ref_clk/ sd_ref_clk cycle to cycle clock jitter (period jitter) cycle-to-cycle at ref clock input t clk_cj ? ? 100 ps ? sd_ref_clk/ sd_ref_clk total reference clock jitter, phase jitter (peak-peak) peak-to-peak jitter at ref clock input t clk_pj ?50 ? +50 ps 2, 3 note: 1 only 100/125/150 mhz have been tested, othe in between values will not work correctly with the rest of the system. 2 in a frequency band from 150 khz to 15 mhz at ber of 10 -12 . 3 total peak to peak deterministic jitter "d j " should be less than or equal to 50 ps. table 54. gen1i/1.5g transmitter (tx) dc specifications parameter symbol min typical max units notes tx differential output voltage v sata_txdiff 400 500 600 mv p-p 1 tx differential pair impedance z sata_txdiffim 85 100 115 ? note: 1 terminated by 50 load. table 53. sata reference clock input requirements (continued) parameter condition symbol min typical max unit notes t h t l ref_clk
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 69 serial ata (sata) table 55 provides the differential transmitter output ac characteristics for the sata interface at gen1i or 1.5 gbits/s transmission. 16.2.2 gen2i/3g transmitter specifications table 56 provides the differential transmitter output dc characteristics for the sata interface at gen2i or 3.0 gbits/s transmission. table 57 provides the differential transmitter output ac characteristics for the sata interface at gen2i or 3.0 gbits/s transmission. table 55. gen1i/1.5g transmitter ac specifications parameter symbol min typical max units notes channel speed t ch_speed ? 1.5 ? gbps ? unit interval t ui 666.4333 666.667 670.2333 ps ? total jitter, data-data 5ui u sata_txtj5ui ? ? 0.355 ui p-p 1 total jitter, data-data 250 ui u sata_txtj250ui ? ? 0.47 ui p-p 1 deterministic jitter, data-data 5ui u sata_txdj5ui ? ? 0.175 ui p-p 1 deterministic jitter, data-data 250 ui u sata_txdj250ui ? ? 0.22 ui p-p 1 note: 1 measured at tx output pins peak to peak phase variation, random data pattern. table 56. gen 2i/3g transmitter dc specifications parameter symbol min typical max units notes tx differential output voltage v sata_txdiff 400 550 700 mv p-p 1 tx differential pair impedance z sata_txdiffim 85 100 115 ? note: 1 terminated by 50 load. table 57. gen 2i/3g transmitter ac specifications parameter symbol min typical max units notes channel speed t ch_speed ?3.0 ?gbps? unit interval t ui 333.2 333.33 335.11 ps ? total jitter f c3db =f baud /10 u sata_txtjfb/10 ?? 0.3ui p-p 1 total jitter f c3db =f baud /500 u sata_txtjfb/500 ? ? 0.37 ui p-p 1
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 70 freescale semiconductor serial ata (sata) 16.3 differential receiver (rx) input characteristics this section discusses the gen1i/1.5g and gen2i/3g differential receiver input ac characteristics. 16.3.1 gen1i/1.5g receiver specifications table 58 provides the gen1i or 1.5 gbits/s differential receiver input dc characteristics for the sata interface. table 59 provides the gen1i or 1.5 gbits/s differential receiver input ac characteristics for the sata interface. total jitter f c3db =f baud /1667 u sata_txtjfb/1667 ? ? 0.55 ui p-p 1 deterministic jitter f c3db =f baud /10 u sata_txdjfb/10 ? ? 0.17 ui p-p 1 deterministic jitter f c3db =f baud /500 u sata_txdjfb/500 ? ? 0.19 ui p-p 1 deterministic jitter f c3db =f baud /1667 u sata_txdjfb/1667 ? ? 0.35 ui p-p 1 note: 1 measured at tx output pins peak to peak phase variation, random data pattern. table 58. gen1i/1.5g receiver input dc specifications parameter symbol min typical max units notes differential input voltage v sata_rxdiff 240 500 600 mv p-p 1 differential rx input impedance z sata_rxseim 85 100 115 ? note: 1 voltage relative to common of either signal comprising a differential pair. table 59. gen 1i/1.5g receiver ac specifications parameter symbol min typical max units notes unit interval t ui 666.4333 666.667 670.2333 ps ? total jitter, data-data 5ui u sata_txtj5ui ? ? 0.43 ui p-p 1 total jitter, data-data 250 ui u sata_txtj250ui ? ? 0.60 ui p-p 1 deterministic jitter, data-data 5ui u sata_txdj5ui ? ? 0.25 ui p-p 1 table 57. gen 2i/3g transmitter ac specifications (continued) parameter symbol min typical max units notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 71 serial ata (sata) 16.3.2 gen2i/3g receiver (rx) specifications table 60 provides the gen2i or 3 gbits/s differential receiver input dc characteristics for the sata interface. table 61 provides the differential receiver output ac characteristics for the sata interface at gen2i or 3.0 gbits/s transmission. deterministic jitter, data-data 250 ui u sata_txdj250ui ? ? 0.35 ui p-p 1 note: 1 measured at tx output pins peak to peak phase variation, random data pattern. table 60. gen2i/3g receiver input dc specifications parameter symbol min typical max units notes differential input voltage v sata_rxdiff 275 500 750 mvp-p 1 differential rx input impedance z sata_rxseim 85 100 115 ? note: 1 voltage relative to common of either signal comprising a differential pair. table 61. gen 2i/3g receiver ac specifications parameter symbol min typical max units notes channel speed t ch_speed ?3.0?gbps? unit interval t ui 333.2 333.33 335.11 ps ? total jitter f c3db =f baud /10 u sata_txtjfb/10 ? ? 0.46 ui p-p 1 total jitter f c3db =f baud /500 u sata_txtjfb/500 ? ? 0.60 ui p-p 1 total jitter f c3db =f baud /1667 u sata_txtjfb/1667 ? ? 0.65 ui p-p 1 deterministic jitter f c3db =f baud /10 u sata_txdjfb/10 ? ? 0.35 ui p-p 1 deterministic jitter f c3db =f baud /500 u sata_txdjfb/500 ? ? 0.42 ui p-p 1 deterministic jitter f c3db =f baud /1667 u sata_txdjfb/1667 ? ? 0.35 ui p-p 1 note: 1 measured at tx output pins peak to peak phase variation, random data pattern. table 59. gen 1i/1.5g receiver ac specifications (continued) parameter symbol min typical max units notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 72 freescale semiconductor timers 17 timers this section describes the dc and ac electrical specifications for the timers of the MPC8377E. 17.1 timers dc electrical characteristics table 62 provides the dc electrical characteristics for the device timers pins, including tin, tout , tgate , and rtc_clk. 17.2 timers ac timing specifications table 63 provides the timers input and output ac timing specifications. figure 46 provides the ac test load for the timers. figure 46. timers ac test load table 62. timers dc electrical characteristics parameter condition symbol min max unit output high voltage i oh = ?6.0 ma v oh 2.4 ? v output low voltage i ol = 6.0 ma v ol ?0.5v output low voltage i ol = 3.2 ma v ol ?0.4v input high voltage ? v ih 2.0 ov dd + 0.3 v input low voltage ? v il ?0.3 0.8 v input current 0 v v in ov dd i in ? 30 a table 63. timers input ac timing specifications 1 parameter symbol 2 min unit timers inputs?minimum pulse width t tiwid 20 ns note: 1 input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2 timers inputs and outputs are asynchronous to any visible clock. timers outputs should be synchronized before use by any external synchronous logic. timers inputs are required to be valid for at least t tiwid ns to ensure proper operation output z 0 = 50 ovdd/2 r l = 50
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 73 gpio 18 gpio this section describes the dc and ac electrical specifications for the gpio of the MPC8377E. 18.1 gpio dc electrical characteristics table 64 provides the dc electrical characteristics for the device gpio. 18.2 gpio ac timing specifications table 65 provides the gpio input and output ac timing specifications. figure 47 provides the ac test load for the gpio. figure 47. gpio ac test load 19 ipic this section describes the dc and ac electrical speci fications for the external interrupt pins of the MPC8377E. table 64. gpio dc electrical characteristics this specification applies when operating at 3.3 v 165 mv supply. parameter condition symbol min max unit output high voltage i oh = ?6.0 ma v oh 2.4 ? v output low voltage i ol = 6.0 ma v ol ?0.5v output low voltage i ol = 3.2 ma v ol ?0.4v input high voltage ? v ih 2.0 ov dd +0.3 v input low voltage ? v il ?0.3 0.8 v input current 0 v v in ov dd i in ? 30 a table 65. gpio input ac timing specifications parameter symbol min unit gpio inputs?minimum pulse width t piwid 20 ns note: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of sys_clkin. timings are measured at the pin. 2. gpio inputs and outputs are asynchronous to any visible clock. gpio outputs should be synchronized before use by any external synchronous logic. gpio inputs are required to be valid for at least t piwid ns to ensure proper operation. output z 0 = 50 ovdd/2 r l = 50
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 74 freescale semiconductor spi 19.1 ipic dc electrical characteristics table 66 provides the dc electrical characteristics for the external interrupt pins of the MPC8377E. 19.2 ipic ac timing specifications table 67 provides the ipic input and output ac timing specifications. 20 spi this section describes the dc and ac electrical specifications for the spi of the MPC8377E. 20.1 spi dc electrical characteristics table 68 provides the dc electrical characteristics for the device spi. table 66. ipic dc electrical characteristics parameter condition symbol min max unit input high voltage ? v ih 2.0 ov dd + 0.3 v input low voltage ? v il ?0.3 0.8 v input current ? i in ?30 a output low voltage i ol = 6.0 ma v ol ?0.5v output low voltage i ol = 3.2 ma v ol ?0.4v note: 1. this table applies for pins irq [0:7], irq_out , mcp_out . 2. irq_out and mcp_out are open drain pins, thus v oh is not relevant for those pins. table 67. ipic input ac timing specifications parameter symbol min unit ipic inputs?minimum pulse width t piwid 20 ns note: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. ipic inputs and outputs are asynchronous to any visible clock. ipic outputs should be synchronized before use by any external synchronous logic. ipic inputs are required to be valid for at least t piwid ns to ensure proper operation when working in edge triggered mode. table 68. spi dc electrical characteristics parameter condition symbol min max unit input high voltage ? v ih 2.0 ov dd + 0.3 v input low voltage ? v il ?0.3 0.8 v input current ? i in ? 30 a output high voltage i oh = ?8.0 ma v oh 2.4 ? v
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 75 spi 20.2 spi ac timing specifications table 69 provides the spi input and output ac timing specifications. figure 48 provides the ac test load for the spi. figure 48. spi ac test load figure 49 through figure 50 represent the ac timing from table 69 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. output low voltage i ol = 8.0 ma v ol ?0.5v output low voltage i ol = 3.2 ma v ol ?0.4v table 69. spi ac timing specifications parameter symbol 1 min max unit spi outputs?master mode (internal clock) delay t nikhov 0.5 6 ns spi outputs?slave mode (external clock) delay t nekhov 28ns spi inputs?master mode (internal clock) input setup time t niivkh 4?ns spi inputs?master mode (internal clock)input hold time t niixkh 0?ns spi inputs?slave mode (external clock) input setup time t neivkh 4?ns spi inputs?slave mode (external clock) input hold time t neixkh 2?ns note: 1 the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhov symbolizes the internal timing (ni) for the time spiclk clock reference (k) goes to the high state (h) until outputs (o) are invalid (x). 2. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. the maximum spiclk input frequency is 66.666 mhz. table 68. spi dc electrical characteristics (continued) parameter condition symbol min max unit output z 0 = 50 ovdd/2 r l = 50
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 76 freescale semiconductor high-speed serial interfaces (hssi) figure 49 shows the spi timing in slave mode (external clock). figure 49. spi ac timing in slave mode (external clock) diagram figure 50 shows the spi timing in master mode (internal clock). figure 50. spi ac timing in master mode (internal clock) diagram 21 high-speed serial interfaces (hssi) the MPC8377E features two serializer/deserializer (serdes) interfaces to be used for high-speed serial interconnect applications. see table 1 for the interfaces supported. this section describes the common portion of serdes dc electrical specifications, which is the dc requirement for serdes reference clocks. the serdes da ta lane?s transmitter and receiver reference circuits are also shown. 21.1 signal terms definition the serdes utilizes differential signaling to transfer data across the serial link. this section defines terms used in the description and specification of differential signals. figure 51 shows how the signals are defined. for illustration purpose, only one serdes lane is used for description. the figure shows waveform for either a transmitter output (sd n _tx and sd n _tx ) or a receiver input (sd n _rx and sd n _rx ). each signal swings between a volts and b volts where a > b. spiclk (input) tn eixkh t neivkh t nekhov input signals: spimosi (see note) output signals: spimiso (see note) note: the clock edge is selectable on spi. spiclk (output) t niixkh t nikhov input signals: spimiso (see note) output signals: spimosi (see note) note: the clock edge is selectable on spi. t niivkh
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 77 high-speed serial interfaces (hssi) using this waveform, the definitions are as follows. to simplify illustration, the following definitions assume that the serdes transmitter and receiver opera te in a fully symmetrical differential signaling environment. ? single-ended swing the transmitter output signals and the receiver input signals sd n _tx, sd n _tx , sd n _rx and sd n _rx each have a peak-to-peak swing of a ? b volts. this is also referred as each signal wire?s single-ended swing. ? differential output voltage, v od (or differential output swing ): the differential output voltage (or swing) of the transmitter, v od , is defined as the difference of the two complimentary output voltages: v sd n _tx ? v sd n _tx . the v od value can be either positive or negative. ? differential input voltage, v id (or differential input swing ): the differential input voltage (or swing) of the receiver, v id , is defined as the difference of the two complimentary input voltages: v sd n _rx ? v sd n _rx . the v id value can be either positive or negative. ? differential peak voltage , v diffp the peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, v diffp = |a ? b| volts. ? differential peak-to-peak , v diffp-p since the differential output signal of the transmitter and the differential input signal of the receiver each range from a ? b to ?(a ? b) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, v diffp-p =2 v diffp = 2 |(a ? b)| volts, which is twice of differential swing in amplitude, or twice of the differential peak. for example, the output differential peak-peak voltage can also be calculated as v tx-diffp-p = 2 |v od |. ? differential waveform the differential waveform is constructe d by subtracting the inverting signal (sd n _tx , for example) from the non-inverting signal (sd n _tx, for example) within a differential pair. there is only one signal trace curve in a differential waveform. the voltage represented in the differential waveform is not referenced to ground. refer to figure 60 as an example for differential waveform. ? common mode voltage, v cm the common mode voltage is equa l to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. in this example, for serdes output, v cm_out =(v sd n _tx +v sd n _tx ) 2=(a+b) 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. in a system, the common mode voltage may often differ from one component?s output to the other?s input. sometimes it may be even different between the receiver input and driver output circuits within the same component. it is also referred as the dc offset in some occasion.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 78 freescale semiconductor high-speed serial interfaces (hssi) figure 51. differential voltage definitions for transmitter or receiver to illustrate these definitions using real values, consider the case of a cml (current mode logic) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5 v and 2.0 v. us ing these values, the peak-to-peak voltage swing of each signal (td or td ) is 500 mv p-p , which is referred as the single-ended swing for each signal. in this example, since the differential signaling environment is fully symmetrical, the transmitter output?s differential swing (v od ) has the same amplitude as each signal?s single-ended swing. the differential output signal ranges between 500 mv and ?500 mv, in other words, v od is 500 mv in one phase and ?500 mv in the other phase. the peak differential voltage (v diffp ) is 500 mv. the peak-to-peak differential voltage (v diffp-p ) is 1000 mv p-p . 21.2 serdes reference clocks the serdes reference clock inputs are applied to an internal pll whose output creates the clock used by the corresponding serdes lanes. the serdes reference clocks inputs are sd1_ref_clk and sd1_ref_clk for both lanes of serdes1, and sd2_ref_clk and sd2_ref_clk for both lanes of serdes2. the following sections describe the serdes re ference clock requirement s and some application information. 21.2.1 serdes reference clock receiver characteristics figure 52 shows a receiver reference diagram of the serdes reference clocks. ? serdes reference clock receiver reference circuit structure ?the sd n _ref_clk and sd n _ref_clk are internally ac-coupled differential inputs as shown in figure 52 . each differential clock input (sd n _ref_clk or sd n _ref_clk ) has a 50 termination to sgnd_srds n (xcorevss) followed by on-chip ac-coupling. ? the external reference clock driver must be able to drive this termination. differential swing, vid or vod = a ? b a volts b volts sd n _tx or sd n _rx sd n _tx or sd n _rx differential peak voltage, vdiffp = |a ? b| differential peak-peak voltage, vdiffpp = 2 vdiffp (not shown) v cm = (a + b)/2
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 79 high-speed serial interfaces (hssi) ? the serdes reference clock input can be eith er differential or single-ended. refer to the differential mode and single-ended mode descri ption below for further detailed requirements. ? the maximum average current requirement that also determines the common mode voltage range ? when the serdes reference clock differential i nputs are dc coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 ma. in this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 ma (refer to th e following bullet for more detail), since the input is ac-coupled on-chip. ? this current limitation sets the maximum common m ode input voltage to be less than 0.4 v (0.4 v 50 = 8 ma) while the minimum common mode input level is 0.1 v above sgnd_srds n (xcorevss). for example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 ma to 16 ma (0?0.8 v), such that each phase of the differential input has a single-ended swing from 0 v to 800 mv with the common mode voltage at 400 mv. ? if the device driving the sd n _ref_clk and sd n _ref_clk inputs cannot drive 50 to sgnd_srds n (xcorevss) dc, or it exceeds the maximum input current limitations, then it must be ac-coupled off-chip. ? the input amplitude requirement ? this requirement is described in detail in the following sections. figure 52. receiver of serdes reference clocks 21.2.2 dc level requirement for serdes reference clocks the dc level requirement for the device serdes re ference clock inputs is different depending on the signaling mode used to connect the clock driver ch ip and serdes reference clock inputs as described below. ? differential mode ? the input amplitude of the differential clock must be between 400 mv and 1600 mv differential peak-peak (or between 200 mv and 800 mv differential peak). in other words, each signal wire of the differential pair must have a single-ended swing less than 800 mv and input amp 50 50 sd n _ref_clk sd n _ref_clk
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 80 freescale semiconductor high-speed serial interfaces (hssi) greater than 200 mv. this requirement is the same for both external dc-coupled or ac-coupled connection. ? for external dc-coupled connection, as described in section 21.2.1, ?serdes reference clock receiver characteristics ,? the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mv and 400 mv. figure 53 shows the serdes reference clock input requirement for dc-coupled connection scheme. ? for external ac-coupled connection, there is no common m ode voltage requirement for the clock driver. since the external ac-coupling capac itor blocks the dc level, the clock driver and the serdes reference clock receiver operate in different command mode voltages. the serdes reference clock receiver in this connec tion scheme has its common mode voltage set to sgnd_srds n . each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (sgnd_srds n ). figure 54 shows the serdes reference clock input requirement for ac-coupled connection scheme. ? single-ended mode ? the reference clock can also be single-ended. the sd _ref_clk input amplitude (single-ended swing) must be between 400 mv and 800 mv p-p (from v min to v max ) with sd n _ref_clk either left unconnected or tied to ground. ?the sd n _ref_clk input average voltage mu st be between 200 mv and 400 mv. figure 55 shows the serdes reference clock input re quirement for single-ended signaling mode. ? to meet the input amplitude requirement, the re ference clock inputs might need to be dc or ac-coupled externally. for the best noise performance, the reference of the clock could be dc or ac-coupled into the unused phase (sd n _ref_clk ) through the same source impedance as the clock input (sd n _ref_clk) in use. figure 53. differential reference clock input dc requirements (external dc-coupled) sd n _ref_clk sd n _ref_clk v max < 800 mv v min > 0 v 100 mv < v cm < 400 mv 200 mv < input amplitude or differential peak < 800 mv
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 81 high-speed serial interfaces (hssi) figure 54. differential reference clock input dc requirements (external ac-coupled) figure 55. single-ended reference clock input dc requirements 21.2.3 interfacing with other differential signaling levels the following list provides information about interf acing with other differential signaling levels. ? with on-chip termination to sgnd_srds n (xcorevss), the differential reference clocks inputs are hcsl (high-speed current steering logic) compatible dc-coupled. ? many other low voltage differential type outputs li ke lvds (low voltage differential signaling) can be used but may need to be ac-coupled due to the limited common mode input range allowed (100 mv to 400 mv) for dc-coupled connection. ? lvpecl outputs can produce signal with too large amplitude and may need to be dc-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to ac-coupling. sd n _ref_clk sd n _ref_clk vcm 200 mv < input amplitude or differential peak < 800 mv 150 v min > v cm ? 400m v fdafdv max < v cm + 400 mv v max < v cm + 400 mv sd n _ref_clk sd n _ref_clk 400 mv < sd n _ref_clk input amplitude < 800 mv 0v
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 82 freescale semiconductor high-speed serial interfaces (hssi) note figure 56 to figure 59 below are for conceptual reference only. due to the fact that clock driver chip's internal structure, output impedance, and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by the clock driver chip vendor are different from what is shown below. they might also vary from one vendor to the other. therefore, freescale semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. the system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the device serdes reference clock receiver requirement provided in this document. figure 56 shows the serdes reference clock connection reference circuits for hcsl type clock driver. it assumes that the dc levels of the clock driver chip is compatible with device serdes reference clock input?s dc requirement. figure 56. dc-coupled differential connection with hcsl clock driver (reference only) figure 57 shows the serdes reference clock connection reference circuits for lvds type clock driver. since lvds clock driver?s common mode voltage is hi gher than the device serdes reference clock input?s allowed range (100 to 400 mv), ac-coupled connecti on scheme must be used. it assumes the lvds 50 50 sd n _ref_clk sd n _ref_clk clock driver 100 differential pwb trace clock driver vendor dependent source termination resistor serdes refer. clk receiver clock driver clk_out clk_out hcsl clk driver chip 33 33 total 50 . assume clock driver?s output impedance is about 16 . MPC8377E clk_out
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 83 high-speed serial interfaces (hssi) output driver features a 50- termination resistor. it also assumes that the lvds transmitter establishes its own common mode level without relying on th e receiver or other external component. figure 57. ac-coupled differential connection with lvds clock driver (reference only) figure 58 shows the serdes reference clock connection refe rence circuits for lvpecl type clock driver. since lvpecl driver?s dc levels (both common mode voltages and output swing) are incompatible with device serdes reference clock input?s dc requirement, ac-coupling has to be used. figure 58 assumes that the lvpecl clock driver?s output impedance is 50 . r1 is used to dc-bias the lvpecl outputs prior to ac-coupling. its value could be ranged from 140 to 240 depending on clock driver vendor?s requirement. r2 is used together with the serdes reference clock receiver?s 50 termination resistor to attenuate the lvpecl output?s differential peak level such that it meets the device serdes reference clock?s differential input amplitude requirement (b etween 200 mv and 800 mv differential peak). for example, if the lvpecl output?s differential peak is 900 mv and the desired serdes reference clock input amplitude is selected as 600 mv, the attenuation factor is 0.67, which requires r2 = 25 . please consult 50 50 sd n _ref_clk sd n _ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvds clk driver chip 10 nf 10 nf MPC8377E
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 84 freescale semiconductor high-speed serial interfaces (hssi) clock driver chip manufacturer to verify whether this connection scheme is comp atible with a particular clock driver chip. figure 58. ac-coupled differential connection with lvpecl clock driver (reference only) figure 59 shows the serdes reference clock connection refe rence circuits for a single-ended clock driver. it assumes the dc levels of the clock driver are comp atible with device serdes reference clock input?s dc requirement. figure 59. single-ended connection (reference only) 21.2.4 ac requirements for serdes reference clocks the clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. phase noise less than 100 khz ca n be tracked by the pll and data recovery loops and is less of a problem. phase noise above 15 mhz is f iltered by the pll. the most problematic phase noise 50 50 sd n _ref_clk sd n _ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvpecl clk driver chip r2 r2 r1 r1 10 nf 10 nf MPC8377E 50 50 sd n _ref_clk sd n _ref_clk 100 differential pwb trace serdes refer. clk receiver clock driver clk_out single-ended clk driver chip 33 total 50 . assume clock driver?s output impedance is about 16 . 50 MPC8377E
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 85 high-speed serial interfaces (hssi) occurs in the 1?15 mhz range. the source impedance of the clock driver should be 50 to match the transmission line and reduce reflections which are a source of noise to the system. table 70 describes some ac parameters common to pci express and sata protocols. figure 60. differential measurement points for rise and fall time figure 61. single-ended measurement points for rise and fall time matching table 70. serdes reference clock common ac parameters at recommended operating conditions with xv dd_srds or xv dd_srds = 1.0 v 5%. parameter symbol min max unit notes rising edge rate rise edge rate 1.0 4.0 v/ns 2, 3 falling edge rate fall edge rate 1.0 4.0 v/ns 2, 3 differential input high voltage v ih 200 ? mv 2 differential input low voltage v il ? ?200 mv 2 rising edge rate (sd n _ref_clk) to falling edge rate (sd n _ref_clk ) matching rise-fall matching ? 20 % 1, 4 note: 1 measurement taken from single ended waveform. 2 measurement taken from differential waveform. 3 measured from ?200 mv to +200 mv on the differential waveform (derived from sd n _ref_clk minus sd n _ref_clk ). the signal must be monotonic through the measurement region for rise and fall time. the 400 mv measurement window is centered on the differential zero crossing. see figure 60 . 4 matching applies to rising edge rate for sd n _ref_clk and falling edge rate for sd n _ref_clk . it is measured using a 200 mv window centered on the median cross point where sdn_ref_clk rising meets sd n _ref_clk falling. the median cross point is used to calculate the voltage thresholds the osc illoscope is to use for the edge rate calculations. the rise edge rate of sd n _ref_clk should be compared to the fall edge rate of sd n _ref_clk , the maximum allowed difference should not exceed 20% of the slowest edge rate. see figure 61 . vih = +200 mv 0.0 v vil = ?200 mv sd n _ref_clk minus sd n _ref_clk rise edge rate fall edge rate t fall t rise sd n _ref_clk v cross median sd n _ref_clk sd n _ref_clk v cross median sd n _ref_clk v cross median ?100 mv v cross median +100 mv
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 86 freescale semiconductor package and pin listings 21.3 serdes transmitter and receiver reference circuits figure 62 shows the reference circuits for serdes data lane?s transmitter and receiver. figure 62. serdes transmitter and receiver reference circuits the dc and ac specification of serdes data lanes are defined in each interface protocol section below in this document based on the application usage: ? section 8, ?ethernet: enhanced three-speed ethernet (etsec)? ? section 15, ?pci express? ? section 16, ?serial ata (sata)? note that an external ac coupling capacitor is requi red for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section. 22 package and pin listings this section details package paramete rs, pin assignments, and dimensions. 22.1 package parameters for the MPC8377E tepbga ii the package parameters are provided in the following list. the package type is 31 mm 31 mm, 689 plastic ball grid array (tepbga ii). package outline 31 mm 31 mm interconnects 689 pitch 1.00 mm module height (typical) 2.0 mm to 2.46 mm (maximum) solder balls 3.5% ag, 96.5% sn ball diameter (typical) 0.60 mm 50 50 receiver transmitter sd1_tx n or sd2_tx n sd1_tx n or sd2_tx n sd1_rx n or sd2_rx n sd1_rx n or sd2_rx n 50 50
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 87 package and pin listings figure 63 shows the mechanical dimensions and bottom surface nomenclature of the tepbga ii package. figure 63. mechanical dimensions and bottom surface nomenclature of the tepbga ii note: 1 all dimensions are in millimeters. 2 dimensioning and tolerancing per asme y14. 5m-1994. 3 maximum solder ball diameter measured parallel to datum a. 4 datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5 parallelism measurement should exclude any effect of mark on top surface of package. 22.2 pinout listings table 71 provides the pin-out listing for the tepbga ii package. table 71. tepbga ii pinout listing signal package pin number pin type power supply notes clock signals clkin k24 i ovdd ?
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 88 freescale semiconductor package and pin listings pci_clk/pci_sync_in c10 i ovdd ? pci_sync_out n24 o ovdd 3 pci_clk0 l24 o ovdd ? pci_clk1 m24 o ovdd ? pci_clk2 m25 o ovdd ? pci_clk3 m26 o ovdd ? pci_clk4 l26 o ovdd ? rtc/pit_clock af11 i ovdd ? ddr sdram memory interface ma0 u3 o gvdd ? ma1 u1 o gvdd ? ma2 t5 o gvdd ? ma3 t3 o gvdd ? ma4 t2 o gvdd ? ma5 t1 o gvdd ? ma6 r1 o gvdd ? ma7 p2 o gvdd ? ma8 p1 o gvdd ? ma9 n4 o gvdd ? ma10 v3 o gvdd ? ma11 m5 o gvdd ? ma12 n1 o gvdd ? ma13 m2 o gvdd ? ma14 m1 o gvdd ? mba0 u5 o gvdd ? mba1 u4 o gvdd ? mba2 m3 o gvdd ? mcas_b w5 o gvdd ? mck_b0 h1 o gvdd ? mck_b1 k1 o gvdd ? mck_b2 v1 o gvdd ? mck_b3 w2 o gvdd ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 89 package and pin listings mck_b4 aa1 o gvdd ? mck_b5 ab2 o gvdd ? mck0 j1 o gvdd ? mck1 l1 o gvdd ? mck2 v2 o gvdd ? mck3 w1 o gvdd ? mck4 y1 o gvdd ? mck5 ab1 o gvdd ? mcke0 m4 o gvdd 3 mcke1 r5 o gvdd 3 mcs_b0 w3 o gvdd ? mcs_b1 p3 o gvdd ? mcs_b2 t4 o gvdd ? mcs_b3 r4 o gvdd ? mdic0 ah8 i/o gvdd 9 mdic1 aj8 i/o gvdd 9 mdm0 b6 o gvdd ? mdm1 b2 o gvdd ? mdm2 e2 o gvdd ? mdm3 e1 o gvdd ? mdm4 y6 o gvdd ? mdm5 ac6 o gvdd ? mdm6 ae6 o gvdd ? mdm7 aj4 o gvdd ? mdm8 l6 o gvdd ? mdq0 a8 i/o gvdd 11 mdq1 a6 i/o gvdd 11 mdq2 c7 i/o gvdd 11 mdq3 d8 i/o gvdd 11 mdq4 a7 i/o gvdd 11 mdq5 a5 i/o gvdd 11 mdq6 a3 i/o gvdd 11 mdq7 c6 i/o gvdd 11 table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 90 freescale semiconductor package and pin listings mdq8 d7 i/o gvdd 11 mdq9 e8 i/o gvdd 11 mdq10 b1 i/o gvdd 11 mdq11 d5 i/o gvdd 11 mdq12 b3 i/o gvdd 11 mdq13 d6 i/o gvdd 11 mdq14 c3 i/o gvdd 11 mdq15 c2 i/o gvdd 11 mdq16 d4 i/o gvdd 11 mdq17 e6 i/o gvdd 11 mdq18 f6 i/o gvdd 11 mdq19 g4 i/o gvdd 11 mdq20 f8 i/o gvdd 11 mdq21 e4 i/o gvdd 11 mdq22 c1 i/o gvdd 11 mdq23 g6 i/o gvdd 11 mdq24 f2 i/o gvdd 11 mdq25 g5 i/o gvdd 11 mdq26 h6 i/o gvdd 11 mdq27 h4 i/o gvdd 11 mdq28 d1 i/o gvdd 11 mdq29 g3 i/o gvdd 11 mdq30 h5 i/o gvdd 11 mdq31 f1 i/o gvdd 11 mdq32 w6 i/o gvdd 11 mdq33 ac1 i/o gvdd 11 mdq34 ac3 i/o gvdd 11 mdq35 ae1 i/o gvdd 11 mdq36 v6 i/o gvdd 11 mdq37 y5 i/o gvdd 11 mdq38 aa4 i/o gvdd 11 mdq39 ab6 i/o gvdd 11 mdq40 ad3 i/o gvdd 11 table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 91 package and pin listings mdq41 ac4 i/o gvdd 11 mdq42 ad4 i/o gvdd 11 mdq43 af1 i/o gvdd 11 mdq44 ae4 i/o gvdd 11 mdq45 ac5 i/o gvdd 11 mdq46 ae2 i/o gvdd 11 mdq47 ae3 i/o gvdd 11 mdq48 ag1 i/o gvdd 11 mdq49 ag2 i/o gvdd 11 mdq50 ag3 i/o gvdd 11 mdq51 af5 i/o gvdd 11 mdq52 ae5 i/o gvdd 11 mdq53 ad7 i/o gvdd 11 mdq54 ah2 i/o gvdd 11 mdq55 ag4 i/o gvdd 11 mdq56 ah3 i/o gvdd 11 mdq57 ag5 i/o gvdd 11 mdq58 af8 i/o gvdd 11 mdq59 aj5 i/o gvdd 11 mdq60 af6 i/o gvdd 11 mdq61 af7 i/o gvdd 11 mdq62 ah6 i/o gvdd 11 mdq63 ah7 i/o gvdd 11 mdqs0 c8 i/o gvdd 11 mdqs1 c4 i/o gvdd 11 mdqs2 e3 i/o gvdd 11 mdqs3 g2 i/o gvdd 11 mdqs4 ab5 i/o gvdd 11 mdqs5 ad1 i/o gvdd 11 mdqs6 ah1 i/o gvdd 11 mdqs7 aj3 i/o gvdd 11 mdqs8 g1 i/o gvdd 11 mecc0/msrcid0 j6 i/o gvdd ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 92 freescale semiconductor package and pin listings mecc1/msrcid1 j3 i/o gvdd ? mecc2/msrcid2 k2 i/o gvdd ? mecc3/msrcid3 k3 i/o gvdd ? mecc4/msrcid4 j5 i/o gvdd ? mecc5/mdval j2 i/o gvdd ? mecc6 l5 i/o gvdd ? mecc7 l2 i/o gvdd ? modt0 n5 o gvdd 6 modt1 u6 o gvdd 6 modt2 m6 o gvdd 6 modt3 p6 o gvdd 6 mras_b aa3 o gvdd ? mvref1 k4 i gvdd 11 mvref2 w4 i gvdd 11 mwe_b y2 o gvdd ? duart interface uart_sin1/msrcid2/lsrcid2 l28 i/o ovdd ? uart_sout1/msrcid0/lsrcid0 l27 o ovdd ? uart_cts_b[1]/msrcid4/lsrcid4 k26 i/o ovdd ? uart_rts_b1 n27 o ovdd ? uart_sin2/msrcid3/ lsrcid3 k27 i/o ovdd ? uart_sout2/msrcid1/lsrcid1 k28 o ovdd ? uart_cts_b[2]/mdval/ldval k29 i/o ovdd ? uart_rts_b[2] l29 o ovdd ? enhanced local bus controller (elbc) interface lad0 e24 i/o lbvdd ? lad1 g28 i/o lbvdd ? lad2 h25 i/o lbvdd ? lad3 f26 i/o lbvdd ? lad4 c26 i/o lbvdd ? lad5 j28 i/o lbvdd ? lad6 f21 i/o lbvdd ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 93 package and pin listings lad7 f23 i/o lbvdd ? lad8 e25 i/o lbvdd ? lad9 e26 i/o lbvdd ? lad10 a23 i/o lbvdd ? lad11 f24 i/o lbvdd ? lad12 g24 i/o lbvdd ? lad13 f25 i/o lbvdd ? lad14 h28 i/o lbvdd ? lad15 g25 i/o lbvdd ? la11/lad16 f27 i/o lbvdd ? la12/lad17 b21 i/o lbvdd ? la13/lad18 a25 i/o lbvdd ? la14/lad19 c28 i/o lbvdd ? la15/lad20 h24 i/o lbvdd ? la16/lad21 e23 i/o lbvdd ? la17/lad22 b28 i/o lbvdd ? la18/lad23 d28 i/o lbvdd ? la19/lad24 a27 i/o lbvdd ? la20/lad25 c25 i/o lbvdd ? la21/lad26 b27 i/o lbvdd ? la22/lad27 h27 i/o lbvdd ? la23/lad28 e21 i/o lbvdd ? la24/lad29 f20 i/o lbvdd ? la25/lad30 d29 i/o lbvdd ? la26/lad31 e20 i/o lbvdd ? la27 h26 o lbvdd ? la28 c29 o lbvdd ? la29 e28 o lbvdd ? la30 b26 o lbvdd ? la31 j25 o lbvdd ? la10/lale h29 o lbvdd ? lbctl a22 o lbvdd ? lclk0 b22 o lbvdd ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 94 freescale semiconductor package and pin listings lclk1 c23 o lbvdd ? lclk2 b23 o lbvdd ? lcs_b0 d25 o lbvdd ? lcs_b1 f19 o lbvdd ? lcs_b2 c27 o lbvdd ? lcs_b3 d24 o lbvdd ? lcs_b4/ldp0 c24 i/o lbvdd ? lcs_b5/ldp1 b29 i/o lbvdd ? la7/lcs_b6/ldp2 e29 i/o lbvdd ? la8/lcs_b7/ldp3 f29 i/o lbvdd ? lfcle/lgpl0 d21 o lbvdd ? lfale/lgpl1 a26 o lbvdd ? lfre_b/lgpl2/loe_b f22 o lbvdd ? lfwp_b/lgpl3 c21 o lbvdd ? lgpl4/lfrb_b/lgta_b/ lupwait/lpbse j29 i/o lbvdd ? la9/lgpl5 g29 o lbvdd ? lsync_in a21 i lbvdd ? lsync_out d23 o lbvdd ? lwe_b0/lfwe0/lbs_b0 e22 o lbvdd ? lwe_b1/lfwe1/lbs_b1 b25 o lbvdd ? lwe_b2/lfwe2/lbs_b2 e27 o lbvdd ? lwe_b3/lfwe3/lbs_b3 f28 o lbvdd ? etsec1/gpio1/gpio2/cfg_reset interface tsec1_col/gpio2[20] af22 i/o lvdd1 ? tsec1_crs/gpio2[2 1 ] ae20 i/o lvdd1 ? tsec1_gtx_clk aj25 o lvdd1 ? tsec1_rx_clk ag22 i lvdd1 ? tsec1_rx_dv ad19 i lvdd1 ? tsec1_rx_er/gpio2[25] ad20 i/o lvdd1 ? tsec1_rxd0 ad22 i lvdd1 ? tsec1_rxd1 ae21 i lvdd1 ? tsec1_rxd2 ae22 i lvdd1 ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 95 package and pin listings tsec1_rxd3 ad21 i lvdd1 ? tsec1_tx_clk aj22 i lvdd1 ? tsec1_tx_en ag23 o lvdd1 ? tsec1_tx_er/cfg_lbmux ah22 i/o lvdd1 ? tsec1_txd0/ cfg_reset_source[0] ad23 i/o lvdd1 ? tsec1_txd1/ cfg_reset_source[1] ae23 i/o lvdd1 ? tsec1_txd2/ cfg_reset_source[2] af23 i/o lvdd1 ? tsec1_txd3/ cfg_reset_source[3] aj24 i/o lvdd1 ? ec_gtx_clk125 ah24 i lvdd1 ? ec_mdc/cfg_clkin_div aj21 i/o lvdd1 ? ec_mdio ah21 i/o lvdd1 ? etsec2/gpio1 interface tsec2_col/gpio1[21]/ tsec1_tmr_trig1 aj27 i/o lvdd2 ? tsec2_crs/gpio1[22]/ tsec1_tmr_trig2 ag29 i/o lvdd2 ? tsec2_gtx_clk af28 o lvdd2 ? tsec2_rx_clk/ tsec1_tmr_clk af25 i lvdd2 ? tsec2_rx_dv/gpio1[23] af26 i/o lvdd2 ? tsec2_rx_er/gpio1[25] ag25 i/o lvdd2 ? tsec2_rxd0/gpio1[16] ae28 i/o lvdd2 ? tsec2_rxd1/gpio1[15] ae29 i/o lvdd2 ? tsec2_rxd2/gpio1[14] ah26 i/o lvdd2 ? tsec2_rxd3/gpio1[13] ah25 i/o lvdd2 ? tsec2_tx_clk/gpio2[24]/ tsec1_tmr_gclk ag28 i/o lvdd2 ? tsec2_tx_en/gpio1[12]/ tsec1_tmr_alarm2 aj26 i/o lvdd2 ? tsec2_tx_er/gpio1[24]/ tsec1_tmr_alarm1 ag26 i/o lvdd2 ? tsec2_txd0/gpio1[20] ah28 i/o lvdd2 ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 96 freescale semiconductor package and pin listings tsec2_txd1/gpio1[19]/ tsec1_tmr_pp1 af27 i/o lvdd2 ? tsec2_txd2/gpio1[18]/ tsec1_tmr_pp2 aj28 i/o lvdd2 ? tsec2_txd3/gpio1[17]/ tsec1_tmr_pp3 af29 i/o lvdd2 ? gpio1 interface gpio1[0]/gtm1_tin1/ gtm2_tin2/dreq0_b p25 i/o ovdd ? gpio1[1]/gtm1_tgate1_b/ gtm2_tgate2_b/dack0_b n25 i/o ovdd ? gpio1[2]/gtm1_tout1_b/ ddone0_b n26 i/o ovdd ? gpio1[3]/gtm1_tin2/ gtm2_tin1/dreq1_b b9 i/o ovdd ? gpio1[4]/gtm1_tgate2_b/ gtm2_tgate1_b/dack1_b n29 i/o ovdd ? gpio1[5]/gtm1_tout2_b/ gtm2_tout1_b/ddone1_b m29 i/o ovdd ? gpio1[6]/gtm1_tin3/ gtm2_tin4/dreq2_b a9 i/o ovdd ? gpio1[7]/gtm1_tgate3_b/ gtm2_tgate4_b/dack2_b b10 i/o ovdd ? gpio1[8]/gtm1_tout3_b/ ddone2_b j26 i/o ovdd ? gpio1[9]/gtm1_tin4/ gtm2_tin3/dreq3_b j24 i/o ovdd ? gpio1[10]/gtm1_tgate4_b/gtm2_t gate3_b/dack3_b j27 i/o ovdd ? gpio1[11]/gtm1_tout4_b/ gtm2_tout3_b/ddone3_b p24 i/o ovdd ? usb/gpio2 interface usbdr_clk/gpio2[23] aj11 i/o ovdd ? usbdr_dir_dppullup/gpio2[9] ag12 i/o ovdd ? usbdr_nxt/gpio2[8] aj10 i/o ovdd ? usbdr_pctl0/gpio2[11]/sd_dat2 af10 i/o ovdd ? usbdr_pctl1/gpio2[22]/sd_dat3 ae9 i/o ovdd ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 97 package and pin listings usbdr_pwrfault/ gpio2[10]/sd_dat1 ag13 i/o ovdd ? usbdr_stp_suspend ah12 o ovdd 12 usbdr_d0_enablen/gpio2[0] ag10 i/o ovdd ? usbdr_d1_ser_txd/gpio2[1] af13 i/o ovdd ? usbdr_d2_vmo_se0/gpio2[2] ag11 i/o ovdd ? usbdr_d3_speed/gpio2[3] ah11 i/o ovdd ? usbdr_d4_dp/gpio2[4] ag9 i/o ovdd ? usbdr_d5_dm/gpio2[5] af9 i/o ovdd ? usbdr_d6_ser_rcv/gpio2[6] ah13 i/o ovdd ? usbdr_d7_drvvbus/gpio2[7] ah10 i/o ovdd ? i 2 c interface iic1_scl c12 i/o ovdd 2 iic1_sda b12 i/o ovdd 2 iic2_scl a10 i/o ovdd 2 iic2_sda a12 i/o ovdd 2 jtag interface tck b13 i ovdd ? tdi e14 i ovdd 4 tdo c13 o ovdd 3 tms a13 i ovdd 4 trst_b e11 i ovdd 4 pci signals pci_ad0 p26 i/o ovdd ? pci_ad1 n28 i/o ovdd ? pci_ad2 p29 i/o ovdd ? pci_ad3 p27 i/o ovdd ? pci_ad4 r26 i/o ovdd ? pci_ad5 r29 i/o ovdd ? pci_ad6 t24 i/o ovdd ? pci_ad7 t25 i/o ovdd ? pci_ad8 r27 i/o ovdd ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 98 freescale semiconductor package and pin listings pci_ad9 p28 i/o ovdd ? pci_ad10 u25 i/o ovdd ? pci_ad11 r28 i/o ovdd ? pci_ad12 u26 i/o ovdd ? pci_ad13 u24 i/o ovdd ? pci_ad14 t29 i/o ovdd ? pci_ad15 v24 i/o ovdd ? pci_ad16 y26 i/o ovdd ? pci_ad17 v28 i/o ovdd ? pci_ad18 aa25 i/o ovdd ? pci_ad19 aa26 i/o ovdd ? pci_ad20 w29 i/o ovdd ? pci_ad21 aa24 i/o ovdd ? pci_ad22 aa27 i/o ovdd ? pci_ad23 ac26 i/o ovdd ? pci_ad24 ab25 i/o ovdd ? pci_ad25 ab24 i/o ovdd ? pci_ad26 aa28 i/o ovdd ? pci_ad27 aa29 i/o ovdd ? pci_ad28 ac24 i/o ovdd ? pci_ad29 ac25 i/o ovdd ? pci_ad30 ab28 i/o ovdd ? pci_ad31 ae24 i/o ovdd ? pci_c_be_b0 t26 i/o ovdd ? pci_c_be_b1 t28 i/o ovdd ? pci_c_be_b2 v29 i/o ovdd ? pci_c_be_b3 y29 i/o ovdd ? pci_devsel_b u28 i/o ovdd 5 pci_frame_b v27 i/o ovdd ? pci_gnt_b0 ae27 i/o ovdd ? pci_gnt_b[1]/cpci_hs_led ac28 o ovdd ? pci_gnt_b[2]/cpci_hs_enum ad27 o ovdd ? pci_gnt_b[3]/pci_pme ac27 o ovdd ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 99 package and pin listings pci_gnt_b[4] ae25 o ovdd ? pci_idsel w28 i ovdd 5 pci_inta_b/irq_out_b ad29 o ovdd 2 pci_irdy_b u29 i/o ovdd 5 pci_par v25 i/o ovdd ? pci_perr_b y25 i/o ovdd 5 pci_req_b0 ae26 i/o ovdd ? pci_req_b[1]/cpci_hs_es ac29 i ovdd ? pci_req_b2 ab29 i ovdd ? pci_req_b3 ad26 i ovdd ? pci_req_b4 w27 i ovdd ? pci_reset_out_b ad28 o ovdd ? pci_serr_b v26 i/o ovdd 5 pci_stop_b w26 i/o ovdd 5 pci_trdy_b y24 i/o ovdd 5 m66en ad15 i ovdd ? programmable interrupt controller (pic) interface mcp_out_b ad14 o ovdd 2 irq_b0/mcp_in_b/gpio2[12] f9 i/o ovdd ? irq_b1/gpio2[13] e9 i/o ovdd ? irq_b2/gpio2[14] f10 i/o ovdd ? irq_b3/gpio2[15] d9 i/o ovdd ? irq_b4/gpio2[16] c9 i/o ovdd ? irq_b5/gpio2[17]/ usbdr_pwrfault ae10 i/o ovdd ? irq_b6/gpio2[18] ad10 i/o ovdd ? irq_b7/gpio2[19] ad9 i/o ovdd ? pmc interface quiesce_b d13 o ovdd ? serdes1 interface l1_sd_imp_cal_rx aj14 i l1_xpadvdd ? l1_sd_imp_cal_tx ag19 i l1_xpadvdd ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 100 freescale semiconductor package and pin listings l1_sd_ref_clk aj17 i l1_xpadvdd ? l1_sd_ref_clk_b ah17 i l1_xpadvdd ? l1_sd_rxa_n aj15 i l1_xpadvdd ? l1_sd_rxa_p ah15 i l1_xpadvdd ? l1_sd_rxe_n aj19 i l1_xpadvdd ? l1_sd_rxe_p ah19 i l1_xpadvdd ? l1_sd_txa_n af15 o l1_xpadvdd ? l1_sd_txa_p ae15 o l1_xpadvdd ? l1_sd_txe_n af18 o l1_xpadvdd ? l1_sd_txe_p ae18 o l1_xpadvdd ? l1_sdavdd_0 aj18 serdes pll power (1.0 or 1.05 v) ?? l1_sdavss_0 ag17 serdes pll gnd ?? l1_xcorevdd ah14, aj16, af17, ah20, aj20 serdes core power (1.0 or 1.05 v) ?? l1_xcorevss ag14, ag15, ag16, ah16, ag18, ag20 serdes core gnd ?? l1_xpadvdd ae16, af16 , ad18 , ae19 , af19 serdes i/o power (1.0 or 1.05 v) ?? l1_xpadvss af14, ae17, af20 serdes i/o gnd ?? serdes2 interface l2_sd_imp_cal_rx c19 i l2_xpadvdd ? l2_sd_imp_cal_tx c15 i l2_xpadvdd ? l2_sd_ref_clk b17 i l2_xpadvdd ? l2_sd_ref_clk_b a17 i l2_xpadvdd ? l2_sd_rxa_n a19 i l2_xpadvdd ? l2_sd_rxa_p b19 i l2_xpadvdd ? l2_sd_rxe_n a15 i l2_xpadvdd ? l2_sd_rxe_p b15 i l2_xpadvdd ? l2_sd_txa_n d18 o l2_xpadvdd ? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 101 package and pin listings l2_sd_txa_p e18 o l2_xpadvdd ? l2_sd_txe_n d15 o l2_xpadvdd ? l2_sd_txe_p e15 o l2_xpadvdd ? l2_sdavdd_0 a16 serdes pll power (1.0 or 1.05 v) ?? l2_sdavss_0 c17 serdes pll gnd ?? l2_xcorevdd a14, b14, d17, b18, b20 serdes core power (1.0 or 1.05 v) ?? l2_xcorevss c14, c16, a18, c18, a20, c20 serdes core gnd ?? l2_xpadvdd d14, e16, f18, d19, e19 serdes i/o power (1.0 or 1.05 v) ?? l2_xpadvss d16, e17, d20 serdes i/o gnd ?? spi interface spiclk/sd_clk ah9 i/o ovdd ? spimiso/sd_dat0 ad11 i/o ovdd ? spimosi/sd_cmd aj9 i/o ovdd ? spisel_b/sd_cd ae11 i ovdd ? system control interface sreset_b ad12 i/o ovdd 2 hreset_b ae12 i/o ovdd 1 poreset_b ae14 i ovdd ? test interface test e10 i ovdd 10 thermal management reserved f15 i ? 13 power supply signals table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 102 freescale semiconductor package and pin listings lvdd1 ac21 , ag21 , ah23 power for etsec 1 i/o (2.5 v, 3.3 v) lvdd1 ? lvdd2 ag24 , ah27 , ah29 power for etsec 2 i/o (2.5 v, 3.3 v) lvdd2 ? lbvdd g20 , d22 , a24 , g26 , d27 , a28 power for elbc (3.3, 2.5, or 1.8 v) lbvdd ? vdd k10 , l10 , m10 , n10 , p10 , r10 , t10 , u10 , v10 , w10 , y10 , k11 , r11 , y11 , k12 , y12 , k13 , y13 , k14 , y14 , k15 , l15 , w15 , y15 , k16 , y16 , k17 , y17 , k18 , y18 , k19 , r19 , y19 , k20 , l20 , m20 , n20 , p20 , r20 , t20 , u20 , v20 , w20 , y20 power for core (1.0 v or 1.5 v) vdd ? gnd ( vss ) a1, aj1 , h2 , n2 , aa2 , ad2 , d3 , r3 , af3 , a4 , f4 , j4 , l4 , v4 , y4 , ab4 , b5 , e5 , p5 , ah5 , k6 , t6 , aa6 , ad6 , ag6 , f7 , j7 , y7 , aj7 , b8 , ae8 , ag8 , g9 , ac9 , b11 , d11 , f11 , l11 , m11 , n11 , p11 , t11 , u11 , v11 , w11 , l12 , m12 , n12 , p12 , r12 , t12 , u12 , v12 , w12 , e12, e13 , l13 , m13 , n13 , p13 , r13 , t13 , u13 , v13 , w13 , ae13 , aj13 , f14 , l14 , m14 , n14 , p14 , r14 , t14 , u14 , v14 , w14 , m15 , n15 , p15 , r15 , t15 , u15 , v15 , l16 , m16 , n16 , p16 , r16 , t16 , u16 , v16 , w16 , l17 , m17 , n17 , p17 , r17 , t17 , u17 , v17 , w17 , l18 , m18 , n18 , p18 , r18 , t18 , u18 , v18 , w18 , l19 , m19 , n19 , p19 , t19 , u19 , v19 , w19 , ac20 , g21 , af21 , c22 , j23 , aa23 , aj23 , b24 , w24 , af24 , k25 , r25 , ad25 , d26 , g27 , m27 , t27 , y27 , ab27 , ag27 , a29 , aj29 ??? avdd_c ad13 power for e300 pll (1.0 or 1.05 v) ?? avdd_l f13 power for elbc pll (1.0 or 1.05 v) ?? avdd_p f12 power for system pll (1.0 v) ?? table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 103 package and pin listings gvdd a2 , d2 , r2 , u2 , ac2 , af2 , aj2 , f3 , h3 , l3 , n3 , y3 , ab3 , b4 , p4 , af4 , ah4 , c5 , f5 , k5 , v5 , aa5 , ad5 , n6 , r6 , aj6 , b7 , e7 , k7 , aa7 , ae7 , ag7 , ad8 power for ddr sdram i/o voltage (2.5 or 1.8 v) gvdd ? ovdd ac10, d10, d12, af12, aj12, k23, y23, r24, ad24, l25, w25, ab26, u27, m28, y28, g10, a11, c11 pci, usb, and other standard (3.3 v) ovdd ? no connect nc f16, f17, ad16, ad17 ? ? 8 pull down pull down b16, ah18 ? ? 7 note: 1 this pin is an open drain signal. a weak pull-up resistor (1 k ) should be placed on this pin to ovdd. 2 this pin is an open drain signal. a weak pull-up resistor (2?10 k ) should be placed on this pin to ovdd. 3 this output is actively driven during reset rather than being released to high impedance during reset. 4 these jtag pins have weak internal pull-up p-fets that are always enabled. 5 this pin should have a weak pull up if the chip is in pci host mode. follow pci specification recommendation and see an3665, mpc837xe design checklist , for more details. 6 these are on die termination pins, used to control ddr2 memories internal termination resistance. 7 this pin must always be tied to gnd using a 0 resistor. 8 this pin must always be left not connected. 9 for ddr2 operation, it is recommended that mdic0 be tied to gnd using an 18.2 resistor and mdic1 be tied to ddr power using an 18.2 resistor. 10 this pin must always be tied low. if it is left floating it may cause the device to malfunction. 11 see an3665, ?mpc837xe design checklist,? for proper ddr termination. 12 this pin must not be pulled down during poreset. 13 open or tie to gnd. table 71. tepbga ii pinout listing (continued) signal package pin number pin type power supply notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 104 freescale semiconductor clocking 23 clocking figure 64 shows the internal distribution of clocks within the MPC8377E. figure 64. MPC8377E clock subsystem the primary clock source for the device can be one of two inputs, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. when the device is configured as a pci host device, clkin is its primary input clock. clkin feeds the pci clock divider ( 2) and the multiplexors for pci_sync_out and pci_clk_out. the cfg_clkin_div configuration input selects whether clkin or clkin/2 is driven out on the pci_sync_out signal. the occr[pcicoe n ] parameters select whether cfg_clkin_ div is driven out on the pci_clk_out n signals. pci_sync_out is connected externally to pci_sync_in to allow the internal clock subsystem to synchronize to the system pci clocks. pci_sync_out must be connected properly to pci_sync_in, with equal delay to all pci agent devices in the system, to allow the device to function. when the device is configured as a pci agent device, pci_clk is the primary input clock. when the device is configured as a pci agent device the clkin signal should be tied to gnd. core pll system pll ddr lbiu lsync_in lsync_out lclk[0:2] mck[0:5] mck [0:5] core_clk e300 core csb_clk to rest clkin csb_clk 6 6 ddr memory local bus pci_clk[0:4] pci_sync_out pci_clk/ clock unit of the device ddr_clk lbiu_clk cfg_clkin_div pci clock pci_sync_in device memory device /n to local bus memory controller to ddr memory controller dll clock div /2 divider 5
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 105 clocking as shown in figure 64 , the primary clock input (frequency) is multiplied up by the system phase-locked loop (pll) and the clock unit to create the coherent system bus clock ( csb_clk ), the internal clock for the ddr controller ( ddr_clk ), and the internal clock for the local bus interface unit ( lbiu_clk ). the csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {pci_sync_in (1 + cfg_clkin_div)} spmf in pci host mode, pci_sync_in (1 + cfg_clkin_div) is the clkin frequency. the csb_clk serves as the clock input to the e300 core. a second pll inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core ( core_clk ). the system and core pll multipliers are selected by the spmf and corepll fields in the reset configuration word low (rcwl) which is loaded at power-on reset or by one of the hard-coded reset options. see chapter 4, ?reset, clocking, and initialization,? in the mpc8379e reference manual for more information on the clock subsystem. the internal ddr_clk frequency is determined by the following equation: ddr_clk = csb_clk (1 + rcwl[ddrcm]) note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the ddr clock divider ( 2) to create the differential ddr memory bus clock outputs (mck and mck ). however, the data rate is the same frequency as ddr_clk . the internal lbiu_clk frequency is determined by the following equation: lbiu_clk = csb_clk (1 + rcwl[lbcm]) note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the lbiu clock divider to create the external local bus clock outputs (lclk[ 0:2]). the elbc clock divider ratio is controlled by lccr[clkdiv]. some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. table 72 specifies which units have a configurable clock frequency. table 72. configurable clock units unit default frequency options etsec1, etsec2 csb_clk/3 off, csb_clk, csb_clk/2, csb_clk/3 esdhc and i 2 c1 1 1 this only applies to i 2 c1 (i 2 c2 clock is not configurable). csb_clk/3 off, csb_clk, csb_clk/2, csb_clk/3 security block csb_clk/3 off, csb_clk, csb_clk/2, csb_clk/3 usb dr csb_clk/3 off, csb_clk, csb_clk/2, csb_clk/3 pci and dma complex csb_clk o ff, csb_clk pci express1, 2 csb_clk/3 off, c sb_clk, csb_clk/2, csb_clk/3 sata1, 2 csb_clk/3 off, csb_clk
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 106 freescale semiconductor clocking table 73 provides the operating frequencies for the tepbga ii package under recommended operating conditions (see table 3 ). 23.1 system pll configuration the system pll is controlled by the rcwl[spmf] pa rameter. the system pll vco frequency depends on rcwl[ddrcm] and rcwl[lbcm]. table 74 shows the multiplication factor encodings for the system pll. note if rcwl[ddrcm] and rcwl[lbcm] are both cleared, the system pll vco frequency = (csb frequency) (system pll vco divider). if either rcwl[ddrcm] or rcwl[lbcm] are set, the system pll vco frequency = 2 (csb frequency) (system pll vco divider). the vco divider needs to be set properly so that the system pll vco frequency is in the range of 400?800 mhz. table 73. operating frequencies for tepbga ii parameter 1 1 the clkin frequency, rcwl[spmf], and rcwl[corepll] settings must be chosen such that the resulting csb_clk , mck, lclk[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. the value of sccr[xcm] must be programmed such that the maximum internal operating frequency of the security core, usb modules, sata, and esdhc will not exceed their respective value listed in this table. minimum operating frequency (mhz) maximum operating frequency (mhz) e300 core frequency ( core_clk ) 333 800 coherent system bus frequency ( csb_clk ) 133 400 ddr2 memory bus frequency (mck) 2 2 the ddr data rate is 2 the ddr memory bus frequency. 125 200 ddr1 memory bus frequency (mck) 2 167 333 local bus frequency (lclk n ) 3 3 the local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on lccr[clkdiv]) which is in turn 1x or 2x the csb_clk frequency (depending on rcwl[lbiucm]). ?133 local bus controller frequency ( lbc_clk )?400 pci input frequency (clkin or pci_clk) 25 66 etsec frequency ? 400 security encryption controller frequency ? 200 usb controller frequency ? 200 esdhc controller frequency ? 200 pci express controller frequency ? 400 sata controller frequency ? 200 note:
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 107 clocking as described in section 23, ?clocking ,? the lbiucm, ddrcm, and spmf parameters in the reset configuration word low and the cfg_clkin_div confi guration input signal select the ratio between the primary clock input (clkin or pci_clk) and the internal coherent system bus clock ( csb_clk ). table 76 and table 77 show the expected frequency values for the csb frequency for select csb_clk to clkin/pci_sync_in ratios. the rcwl[svcod] denotes the system pll vco internal frequency as shown in table 75 . table 74. system pll multiplication factors rcwl[spmf] system pll multiplication factor 0000 reserved 0001 reserved 0010 2 0011 3 0100 4 0101 5 0110 6 0111?1111 7 to 15 table 75. system pll vco divider rcwl[svcod] vco division factor 00 4 01 8 10 2 11 1 table 76. csb frequency options for host mode cfg_clkin_div at reset 1 spmf csb_clk : input clock ratio 2 input clock frequency (mhz) 2 25 33.33 66.67 csb_clk frequency (mhz) ? high 0010 2 : 1 133 high 0011 3 : 1 100 ? high 0100 4 : 1 100 133 ? high 0101 5 : 1 125 167 ?
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 108 freescale semiconductor clocking high 0110 6 : 1 ? high 0111 7 : 1 high 1000 8 : 1 high 1001 9 : 1 high 1010 10 : 1 high 1011 11 : 1 high 1100 12 : 1 high 1101 13 : 1 high 1110 14 : 1 high 1111 15 : 1 1 cfg_clkin_div select the ratio between clkin and pci_sync_out. 2 clkin is the input clock in host mode; pci_clk is the input clock in agent mode. table 77. csb frequency options for agent mode cfg_clkin_div at reset 1 spmf csb_clk : input clock ratio 2 input clock frequency (mhz) 2 25 33.33 66.67 csb_clk frequency (mhz) ? low 0010 2 : 1 133 low 0011 3 : 1 100 ? low 0100 4 : 1 ? 133 ? low 0101 5 : 1 125 ? ? table 76. csb frequency options for host mode (continued) cfg_clkin_div at reset 1 spmf csb_clk : input clock ratio 2 input clock frequency (mhz) 2 25 33.33 66.67 csb_clk frequency (mhz) ?
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 109 clocking 23.2 core pll configuration rcwl[corepll] selects the ratio between the internal coherent system bus clock ( csb_clk ) and the e300 core clock ( core_clk ). table 78 shows the encodings for rcwl[corepll]. corepll values that are not listed in table 78 should be considered as reserved. note core vco frequency = core frequency vco divider vco divider has to be set properly so that the core vco frequency is in the range of 800?1600 mhz. low 0110 6 : 1 150 200 low 0111 7 : 1 175 233 low 1000 8 : 1 200 266 low 1001 9 : 1 225 300 low 1010 10 : 1 250 333 low 1011 11 : 1 275 low 1100 12 : 1 300 low 1101 13 : 1 325 low 1110 14 : 1 low 1111 15 : 1 1 cfg_clkin_div doubles csb_clk if set high. 2 clkin is the input clock in host mode; pci_clk is the input clock in agent mode. table 78. e300 core pll configuration rcwl[corepll] core_clk : csb_clk ratio vco divider 1 0?1 2?5 6 nn 0000 0 pll bypassed (pll off, csb_clk clocks core directly) pll bypassed (pll off, csb_clk clocks core directly) 11 nnnn nn/a n/a 00 0001 01:1 2 01 0001 01:1 4 10 0001 01:1 8 table 77. csb frequency options for agent mode (continued) cfg_clkin_div at reset 1 spmf csb_clk : input clock ratio 2 input clock frequency (mhz) 2 25 33.33 66.67 csb_clk frequency (mhz) ?
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 110 freescale semiconductor clocking 23.3 suggested pll configurations table 79 shows suggested pll configurations for different input clocks (lbcm = 0). 00 0001 1 1.5:1 2 01 0001 1 1.5:1 4 10 0001 1 1.5:1 8 00 0010 02:1 2 01 0010 02:1 4 10 0010 02:1 8 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 10 0010 1 2.5:1 8 00 0011 03:1 2 01 0011 03:1 4 10 0011 03:1 8 00 0011 1 3.5:1 2 01 0011 1 3.5:1 4 10 0011 1 3.5:1 8 00 0100 04:1 2 01 0100 04:1 4 10 0100 04:1 8 note: 1 core vco frequency = core frequency vco divider. note that vco divider has to be set properly so that the core vco frequency is in the range of 800?1600 mhz. table 79. example clock frequency combinations elbc 1 e300 core 1 ref 1 lbcm ddrcm svcod spmf sys vco 1, 2 csb 1 ,3 ddr data rate 1, 4 /2 /4 /8 1 1.5 2 2.5 3 25.0 0 1 2 5 500 125 250 62.531.315.6????375 25.0 0 1 2 6 600 150 300 75 6 37.5 18.8 ? ? ? 375 450 33.3 0 1 2 5 667 167 333 83.3 6 41.6 20.8 ? ? 333 416 500 33.3 0 1 2 4 533 133 267 66.7 33.3 16.7 ? ? ? 333 400 table 78. e300 core pll configuration (continued) rcwl[corepll] core_clk : csb_clk ratio vco divider 1 0?1 2?5 6
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 111 thermal 24 thermal this section describes the thermal specifications of the MPC8377E. 24.1 thermal characteristics table 80 provides the package thermal characteristics for the 689 31 31mm tepbga ii package. 48.0 0 1 2 3 576 144 288 72 6 36 18 ? ? ? 360 432 66.7 0 1 2 2 533 133 266 66.7 33.3 16.7 ? ? ? 333 400 25.0 0 0 4 8 800 200 200 100 6 50 25 ? ? 400 500 600 33.3 0 0 2 8 533 266.7 267 133 6 66.7 33.3 ? 400 533 667 800 50.0 0 0 4 4 800 200 200 100 6 50 25 ? ? 400 500 600 50.0 0 0 2 8 800 400 400 5 ? 100 6 50 ? 600 800 ? ? 66.7 0 0 2 4 533 266.7 267 133 6 66.7 33.3 ? 400 533 667 800 66.7 0 0 2 5 667 333 333 ? 83.3 6 41.6 333 500 667 ? ? 66.7 0 0 2 6 800 400 400 5 ? 100 6 50 400 600 800 ? ? note: 1 values in mhz. 2 system pll vco range: 400?800 mhz. 3 csb frequencies less than 133 mhz will not support gigabit ethernet rates. 4 minimum data rate for ddr2 is 250 mhz and for ddr1 is 167 mhz. 5 applies to ddr2 only. 6 applies to elbc pll-enabled mode only. table 80. package thermal characteristics for tepbga ii parameter symbol value unit notes junction-to-ambient natural convection on single layer board (1s) r ja 21 c/w 1, 2 junction-to-ambient natural convection on four layer board (2s2p) r ja 15 c/w 1, 2, 3 junction-to-ambient (at 200 ft/min) on single layer board (1s) r jma 16 c/w 1, 3 junction-to-ambient (at 200 ft/min) on four layer board (2s2p) r jma 12 c/w 1, 3 junction-to-board thermal r jb 8 c/w 4 junction-to-case thermal r jc 6 c/w 5 table 79. example clock frequency combinations (continued) elbc 1 e300 core 1 ref 1 lbcm ddrcm svcod spmf sys vco 1, 2 csb 1 ,3 ddr data rate 1, 4 /2 /4 /8 1 1.5 2 2.5 3
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 112 freescale semiconductor thermal 24.2 thermal management information for the following sections, p d = (v dd i dd ) + p i/o where p i/o is the power dissipation of the i/o drivers. 24.2.1 estimation of junction temperature with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + ( r ja p d ) where: t j = junction temperature ( c) t a = ambient temperature for the package ( c) r ja = junction to ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the junction to ambient thermal resistance is an indus try-standard value that provides a quick and easy estimation of thermal performance. generally, the value obtained on a single layer board is appropriate for a tightly packed printed circuit board. the value obtaine d on the board with the internal planes is usually appropriate if the board has low power dissipation a nd the components are well separated. test cases have demonstrated that errors of a factor of two (in the quantity t j ? t a ) are possible. 24.2.2 estimation of junction temperature with junction-to-board thermal resistance note the heat sink cannot be mounted on the package. junction-to-package natural convection on top jt 6 c/w 6 note: 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 per jedec jesd51-2 with the single layer board horizontal. board meets jesd51-9 specification. 3 per jedec jesd51-6 with the board horizontal. 4 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. table 80. package thermal characteristics for tepbga ii (continued) parameter symbol value unit notes
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 113 thermal the thermal performance of a device cannot be adequa tely predicted from the junction to ambient thermal resistance. the thermal performance of any component is strongly dependent on the power dissipation of surrounding components. in addition, the ambient temper ature varies widely within the application. for many natural convection and especially closed box a pplications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. specifying the local ambient conditions explicitly as the board te mperature provides a more precise description of the local ambient conditions that determine the temperature of the device. at a known board temperature, the junction temp erature is estimated using the following equation: t j = t a + ( r jb p d ) where: t a = ambient temperature for the package ( c) r jb = junction to board thermal resistance ( c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the ai r can be ignored, acceptable predictions of junction temperature can be made. the application board shoul d be similar to the thermal test condition: the component is soldered to a board with internal planes. 24.2.3 experimental determination of junction temperature note the heat sink cannot be mounted on the package. to determine the junction temperature of the device in the application after prototypes are available, use the thermal characterization parameter ( jt ) to determine the junction temperature and a measure of the temperature at the top center of the package case using the following equation: t j = t t + ( jt p d ) where: t j = junction temperature ( c) t t = thermocouple temperature on top of package ( c) jt = junction to ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per the jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the p ackage case. the thermocouple should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 24.2.4 heat sinks and junction-to-case thermal resistance for the power values the device is expected to operate at, it is anticipated that a heat sink will be required. a preliminary estimate of heat sink performance can be obtained from the following first first-cut
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 114 freescale semiconductor thermal approach. the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r ja = junction to ambient thermal resistance ( c/w) r jc = junction to case thermal resistance ( c/w) r ca = case to ambient thermal resistance ( c/w) r jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case to ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface ma terial, the mounting arrangement on printed circuit board, or change the thermal dissipation on th e printed circuit board surrounding the device. this first-cut approach overestimates the heat sink size required, since heat flow through the board is not accounted for, which can be as much as one-third to one-half of the power generated in the package. accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling through the package and board and the convection cooling due to the air moving through th e application. simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. more detailed thermal models can be made available on request. the thermal performance of devices with heat sinks has been simulated with a few commercially available heat sinks. the heat sink choice is determined by th e application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. because of the wide variety of application environments, a single standard heat sink applicable to all cannot be specified.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 115 thermal table 81 shows the heat sink thermal resistance for tepbga ii package with heat sinks, simulated in a standard jedec environment, per jesd 51-6. heat sink vendors include the following: aavid thermalloy www.aavidthermalloy.com alpha novatech www.alphanovatech.com international electronic research corporation (ierc) www.ctscorp.com millennium electronics (mei) www.mei-thermal.com table 81. thermal resistance with heat sink in open flow (tepbga ii) heat sink assuming thermal grease air flow thermal resistance ( /w) aavid 30 30 9.4 mm pin fin natural convection 13.1 0.5 m/s 10.6 1 m/s 9.3 2 m/s 8.2 4 m/s 7.5 aavid 31 35 23 mm pin fin natural convection 11.1 0.5 m/s 8.5 1 m/s 7.7 2 m/s 7.2 4 m/s 6.8 aavid 43 41 16.5mm pin fin natural convection 11.3 0.5 m/s 9.0 1 m/s 7.8 2 m/s 7.0 4 m/s 6.5 wakefield, 53 53 25 mm pin fin natural convection 9.7 0.5 m/s 7.7 1 m/s 6.8 2 m/s 6.4 4 m/s 6.1
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 116 freescale semiconductor thermal tyco electronics chip coolers? www.chipcoolers.com wakefield engineering www.wakefield.com interface material vendors include the following: chomerics, inc. www.chomerics.com dow-corning corporation dow-corning electronic materials www.dowcorning.com shin-etsu microsi, inc. www.microsi.com the bergquist company www.bergquistcompany.com 24.3 heat sink attachment the device requires the use of heat sinks. when heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip. the spri ng clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board , or to a plastic stiffener. avoid attachment forces that can lift the edge of the package or peel the p ackage from the board. such peeling forces reduce the solder joint lifetime of the package. the recommended maximum compressive force on the top of the package is 10 lb force (4.5 kg force). any adhesive att achment should attach to painted or plastic surfaces, and its performance should be verified under the application requirements. 24.3.1 experimental determination of the junction temperature with a heat sink when a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimize the size of the clearance to minimize the change in thermal performance caused by removing part of the thermal inte rface to the heat sink. because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. from this case temperature, the junction temperature is determined from the junction to case thermal resistance. t j = t c + ( r jc p d ) where: t j = junction temperature ( c) t c = case temperature of the package ( c)
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 117 system design information r jc = junction to case thermal resistance ( c/w) p d = power dissipation (w) 25 system design information this section provides electrical and thermal design recommendations for successful application of the MPC8377E. 25.1 pll power supply filtering each of the plls listed above is provided with power through independent power supply pins. the av dd level should always be equivalent to v dd , and preferably these voltages will be derived directly from v dd through a low frequency filter scheme. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide five independent filter circuits as illustrated in figure 65 , one to each of the five av dd pins. by providing independent filters to each pll, the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as cl ose as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd pin, which is on the periphery of pack age, without the inductance of vias. figure 65 shows the pll power supply filter circuit. figure 65. pll power supply filter circuit 25.2 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the device can generate transient power surges and high frequency noise in its power suppl y, especially while driving large capacitive loads. this noise must be prevented from reaching other co mponents in the device system, and the device itself requires a clean, tightly regulated source of power. th erefore, it is recommended that the system designer place at least one decoupling capacitor at each vdd, ovdd, gvdd, and lvdd pins of the device. these decoupling capacitors should receive their power from separate vdd, ovdd, gvdd, lvdd, and gnd power planes in the pcb, utilizing short traces to min imize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may surround the part. vdd avdd (or l2avdd) 2.2 f 2.2 f gnd low esl surface mount capacitors 10
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 118 freescale semiconductor system design information these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd, ovdd, gvdd, and lvdd planes, to en able quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 25.3 connection recommendations to ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate signal level. unused active low inputs should be tied to ovdd, gvdd, or lvdd as required. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external vdd, gvdd, lvdd, ovdd, and gnd pins of the device. 25.4 output buffer dc impedance the device drivers are characterized over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ovdd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 66 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 66. driver impedance measurement ovdd ognd r p r n pad data sw1 sw2
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 119 ordering information the value of this resistance and the strength of the driver?s current source can be found by making two measurements. first, the output voltage is measured while driving logic 1 without an external differential termination resistor. the measured voltage is v 1 = r source i source . second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value r term . the measured voltage is v 2 =(1/(1/r 1 +1/r 2 )) i source . solving for the output impedance gives r source = r term (v 1 /v 2 ? 1). the drive current is then i source =v 1 /r source . table 82 summarizes the signal impedance targets. the driver impedance are targeted at minimum v dd , nominal ov dd , 105 c. 25.5 configuration pin muxing the device provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see cu stomer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when poreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal func tion. careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. 25.6 pull-up resistor requirements the device requires high resistance pull-up resistors (10 k is recommended) on open drain type pins including i 2 c pins, ethernet management mdio pin and ipic interrupt pins. for more information on required pull-up resistors and the connections required for the jtag interface, see an3665, ?mpc837xe design checklist.? 26 ordering information ordering information for the parts fully covered by this specification document is provided in section 26.1, ?part numbers fully addressed by this document.? table 82. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci signals (not including pci output clocks) pci output clocks (including pci_sync_out) ddr dram symbol unit r n 42 target 25 target 42 target 20 target z 0 w r p 42 target 25 target 42 target 20 target z 0 w differential na na na na z diff w note: nominal supply voltages. see ta b l e 2 , t j = 105 c.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 120 freescale semiconductor ordering information 26.1 part numbers fully addressed by this document table 83 provides the freescale part numbering nomenclat ure for the MPC8377E. note that the individual part numbers correspond to a maximum processor core frequency. for available fr equencies, contact your local freescale sales office. in addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify sp ecial application conditions. each part number also contains a revision code which refers to the die mask revision number. table 84 lists the available core and ddr data rate frequency combinations. table 83. part numbering nomenclature mpc 8377 ec zq af d a product code part identifier encryption acceleration temperature range 1 package 2 e300 core frequency 3, 4 ddr data rate revision level mpc 8377 blank = not included e = included blank = 0 c (t a ) to 125 c (t j ) c = ?40 c (t a ) to 125 c (t j ) vr = pb-free 689 tepbga ii al = 667 mhz aj = 533 mhz ag = 400 mhz an = 800 mhz g = 400 mhz f = 333 mhz d = 266 mhz contact local freescale sales office note: 1 contact local freescale office on availability of parts with an extended temperature range. 2 see section 22, ?package and pin listings,? for more information on the available package type. 3 processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies. 4 an 800 mhz device is not supported in extended temperature (?40 c to 125 c). table 84. available part s (core/ddr data rate) MPC8377E mpc8378e mpc8379e 800 mhz/400 mhz 800 mhz/400 mhz 800 mhz/400 mhz 667 mhz/400 mhz 667 mhz/400 mhz 667 mhz/400 mhz 533 mhz/333 mhz 533 mhz/333 mhz 533 mhz/333 mhz 400 mhz/266 mhz 400 mhz/266 mhz 400 mhz/266 mhz
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 121 ordering information table 85 shows the svr and pvr settings by device. 26.2 part marking parts are marked as in the example shown in figure 67 . figure 67. freescale part marking for tepbga ii devices table 85. svr and pvr settings by product revision device package svr pvr rev 1.0 rev. 2.1 rev. 1.0 rev. 2.1 mpc8377 tepbga ii 0x80c7_0010 0x80c7_0021 0x8086_1010 0x8086_1011 MPC8377E 0x80c6_0010 0x80c6_0021 mpc8378 0x80c5_0010 0x80c5_0021 mpc8378e 0x80c4_0010 0x80c4_0021 mpc8379 0x80c3_0010 0x80c3_0021 mpc8379e 0x80c2_0010 0x80c2_0021 mpcnnnnetppaaar core/platform mhz atwlyyww ccccc tepbga ii *mmmmm ywwlaz notes : atwlyyww is the traceability code. ccccc is the country code. mmmmm is the mask number. ywwlaz is the assembly traceability code.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 122 freescale semiconductor document revision history 27 document revision history table 86 provides a revision history for this hardware specification. table 86. document revision history revision date substantive change(s) 2 10/2009 ? in ta ble 3 , ?recommended operating conditions,? added ?operating temperature range? values. ?in ta b l e 5 , ?MPC8377E power dissipation 1 ,? corrected maximal application for 800/400 mhz to 4.3 w. ?in ta ble 5 , ?MPC8377E power dissipation 1 ,? added a column for ?typical application at t j =65 c (w)?. ?in ta ble 5 , ?MPC8377E power dissipation 1 ,? added a column for ?sleep power at t j =65 c (w)?. ?in ta ble 1 0 , removed overbar from cfg_clkin_div. ?in ta b l e 1 6 , ?current draw characteristics for mv ref ,? updated i mvref maximum value for both ddr1 and ddr2 to 600 and 400 a, respectively. also, updated note 1 and added note 2. ?in tab le 1 9 , ?ddr1 and ddr2 sdram input ac timing specifications,? column headings renamed to ?min? and ?max?. footnote 2 updated to state ?t is the mck clock period?. ?in ta ble 1 9 , ?ddr1 and ddr2 sdram input ac timing specifications,? and ta ble 2 0 , ?ddr1 and ddr2 sdram output ac timing specifications,? clarified that the frequency parameters are data rates. ?in ta ble 2 8 , ?rmii transmit ac timing specifications,? updated t rmtdx i to 2.0 ns. ?in ta ble 5 9 , gen 1i/1.5g receiver ac specifications,? and ta b l e 6 1 , gen 2i/3g receiver ac specifications,? corrected titles from ?transmitter? to ?receiver?. ?in ta ble 7 1 , ?tepbga ii pinout listing ,? removed pin therm0; it is now reserved. also added 1.05 v to vdd pin. ?in ta ble 7 3 , ?operating frequencies for tepbga ii ,? corrected ?ddr2 memory bus frequency (mck)? range to 125?200. ?in ta ble 7 8 , ?e300 core pll configuration,? added 3.5:1 and 4:1 core_clk: csb_clk ratio options. ?in ta ble 7 9 , ?example clock frequency combinations,? updated column heading to ?ddr data rate? . ?in section 20.2, ?spi ac timing specifications,? corrected t nikhox and t nekhox to t nikhov and t nekhov , respectively. 1 02/2009 ? in tab le 3 , ?recommended operating conditions,? added two new rows for 800 mhz, and created two rows for serdes. in addition, changed 666 to 667 mhz. ?in ta ble 5 , ?MPC8377E power dissipation 1 ,? added notes 4 and 5. in addition, changed 666 to 667 mhz. ?in tab le 1 2 , ?ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8 v,? ta b l e 2 0 , ?ddr1 and ddr2 sdram output ac timing specifications,? and ta b l e 7 1 , ?tepbga ii pinout listing,? added footnote to references to mvref, mdq, and mdqs, referencing an3665, mpc837xe design checklist . ?in ta ble 2 0 , updated t ddkhcx minimum value for 333 mhz to 2.40. ?in ta ble 7 1 , ?tepbga ii pinout listing,? added footnote to usbdr_stp_suspend and modified footnote 10 and added footnote 13. ?in ta ble 7 3 , ?operating frequencies for tepbga ii,? changed 667 to 800 mhz for core_clk . ?in ta ble 7 9 , ?example clock frequency combinations,? added 800 mhz cells for e300 core. ? updated part numbering information in af column in ta b l e 8 3 , ?part numbering nomenclature.? in addition, modified extended temperature information in notes 1 and 4. ?in ta ble 8 4 , ?available parts (core/ddr data rate),? added new row for 800/400 mhz. 0 12/2008 initial public release.
MPC8377E powerquicc ? ii pro processor hardware specifications, rev. 2 freescale semiconductor 123 document revision history this page intentionally left blank
document number: MPC8377Eec rev. 2 10/2009 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ieee 802.3, 802.3u, 802.3x, 802.3z, 802.3au, 802.3ab, 1588 are registered trademarks of the institute of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2009. all rights reserved.

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